DVI Codec, 17DVI Controller Connections | Xilinx ML605 instruction

Detailed Description

14. DVI Codec

The ML605 features a DVI connector (P3) to support an external video monitor. The DVI circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit color. The video interface chip drives both the digital and analog signals to the DVI connector. A DVI monitor can be connected to the board directly. A VGA monitor can also be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel CH7301C is controlled by way of the video IIC bus.

The DVI connector (Table 1-17) supports the IIC protocol to allow the board to read the monitor's configuration parameters. These parameters can be read by the FPGA using the DVI IIC bus (see “15. IIC Bus,” page 42).

Table 1-17:DVI Controller Connections

	U1 FPGA Pin	Schematic Net Name	U38 Chrontel CH7301C

			Pin Number	Pin Name
			Pin Number	Pin Name

	AJ19	DVI_D0	63	D0

	AH19	DVI_D1	62	D1

	AM17	DVI_D2	61	D2

	AM16	DVI_D3	60	D3

	AD17	DVI_D4	59	D4

	AE17	DVI_D5	58	D5

	AK18	DVI_D6	55	D6

	AK17	DVI_D7	54	D7

	AE18	DVI_D8	53	D8

	AF18	DVI_D9	52	D9

	AL16	DVI_D10	51	D10

	AK16	DVI_D11	50	D11

	AD16	DVI_DE	2	DE

	AN17	DVI_H	4	H

	AP17	DVI_RESET_B_LS	13	RESET_B

	AD15	DVI_V	5	V

	AC17	DVI_XCLK_N	56	XCLK_N

	AC18	DVI_XCLK_P	57	XCLK_P

	No Connect	DVI_GPIO0	8	GPIO0

	No Connect	DVI_GPIO1	7	GPIO1

ML605 Hardware User Guide	www.xilinx.com	41
UG534 (v1.2.1) January 21, 2010

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Xilinx ML605 manual DVI Codec, 17DVI Controller Connections, U38 Chrontel CH7301C

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm WDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential Smarefclkp SMA PinSmarefclkn ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs Gpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin Switch Pin User DIP Switch Usersmagpiop User SMA GpioUsersmagpion J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections Detailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References