Kb NV Memory, Iicsdamain SDA, Iicsclmain SCL | Xilinx ML605 guide

Chapter 1: ML605 Evaluation Board

8 Kb NV Memory

IIC SCL MAIN

IIC SDA MAIN

The ML605 hosts an 8 Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U6). The IIC address of U7 is 0b1010100, and U6 is not write protected (WP pin 7 is tied to GND).

The IIC memory is shown in Figure 1-15.

VCC3V3

1

1

2

R414

2

0 5%

6

U6

VCC3V3

VCC3V3

1

2

5

SCL

7

R413 0

5% 1/16W

R414 0

5% 1/16W

SDA

WP

1

C65

2

A1

VCC

8

2

10V

1

A0

X5R

0.1UF

3

A2

GND

4

M24C08-WDW6TP

1IIC Address = 0b1010100

R305

DNP 1%

2 1/16W

UG534_15_072109

Figure 1-15: IIC Memory U6

Table 1-18:IIC Memory Connections

	FPGA U1 Pin	Schematic Net Name	IIC Memory U6

			Pin Number	Pin Name
			Pin Number	Pin Name

	Not Applicable	Tied to GND	1	A0

	Not Applicable	Tied to GND	2	A1

	Not Applicable	Pulled up (0 ohm) to VCC3V3	3	A2

	N10	IIC_SDA_MAIN	5	SDA

	P11	IIC_SCL_MAIN	6	SCL

	Not Applicable	Tied to GND	7	WP

References

See the ST Micro M24C08 Data Sheet for more information. [Ref 31]

In addition, see the Xilinx XPS IIC Bus Interface (v2.00a) Data Sheet. [Ref 21]

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		UG534 (v1.2.1) January 21, 2010

Image 44

Xilinx ML605 manual Kb NV Memory, Iicsdamain SDA, Iicsclmain SCL

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information Features ML605 Evaluation BoardSMA IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram ML605 Features FeatureDetailed Description DDR3 Sodimm WDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga 2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga Bank MB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkp SMA PinSmarefclkn Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 12Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 PHYRXD4 RXD4PHYRXD5 RXD5 Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs User I/O Fpga Init and Done LEDsControlled LED Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Gpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin User DIP Switch Switch Pin Usersmagpiop User SMA GpioUsersmagpion LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin Detailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch Onboard Power Regulation 28ML605 Onboard Power Regulators UCD9240PFC VccintfpgaVccaux UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References