Virtex-6 XC6VLX240T-1FFG1156 Fpga, Configuration | Xilinx ML605

						Detailed Description

			Table 1-1:		ML605 Features (Cont’d)

			Number		Feature	Notes	Schematic
			Number		Feature	Notes	Page
							Page

					Switches		13, 25, 39

					a. Power On/Off	Slide switch	39

					b. FPGA_PROG_B	active-Low	13
			18		pushbutton	active-Low	13
			18		pushbutton

					c. System ACE CF Image	4-pole DIP switch (active-High)	25
					Select	4-pole DIP switch (active-High)	25
					Select

					d. Mode Switch	6-pole DIP switch (active-High)	25

			19		FMC - HPC connector	Samtec ASP-134486-01	16 -19

			20		FMC - LPC connector	Samtec ASP-134603-01	20

					Power management		35 - 44

					a. PMBus controllers	2 x TI UCD9240PFC	35, 40

					b. Voltage regulators	2 x PTD08A020W, 3 x PTD08A010W	36-38, 43,
						2 x PTD08A020W, 3 x PTD08A010W	44
			21				44
			21
					c. 12V power input	6-pin Molex mini-fit connector	39
					connector	6-pin Molex mini-fit connector	39
					connector

					d. 12V power input	4-pin ATX disk type connector	39
					connector	4-pin ATX disk type connector	39
					connector

			22		System Monitor Interface	2x6 DIP male pin header	34
			22		connector	2x6 DIP male pin header	34
					connector

			23		System ACE Error DS30 LED	Jumper on = enable LED	13
			23		disable jumper J69	Jumper off = disable LED	13
					disable jumper J69	Jumper off = disable LED

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

AVirtex-6 XC6VLX240T-1FFG1156 FPGA is installed on the embedded development board.

Keep-Out areas and drill holes are defined around the FPGA to support an Ironwood

Electronics SG-BGA-6046 FPGA socket.

References

See the Virtex-6 FPGA Data Sheet. [Ref 4]

Configuration

The ML605 supports configuration in the following modes:

•Slave SelectMAP (using Platform Flash XL with the onboard 47 MHz oscillator)

•Master BPI-Up (using Linear BPI Flash device)

•JTAG (using the included USB-A to Mini-B cable)

•JTAG (using System ACE CF and CompactFlash card)

ML605 Hardware User Guide	www.xilinx.com	13
UG534 (v1.2.1) January 21, 2010

Image 13

Xilinx ML605 manual Virtex-6 XC6VLX240T-1FFG1156 Fpga, Configuration

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential Smarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP Switch Usersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References