Xilinx manual ML605 Evaluation Board ML605 Features Cont’d, Sgmii, WDW6TP

Chapter 1: ML605 Evaluation Board

Table 1-1:	ML605 Features (Cont’d)
Number	Feature	Notes	Schematic
			Page
	Clock generation	200 MHz OSC, oscillator socket, SMA	30
		connectors
	a. 200 MHz oscillator (on	Epson 200 MHz 2.5V LVDS OSC	30
	backside)
7
	b. Oscillator socket, single-	MMD Components 66 MHz 2.5V	30
	ended
	c. SMA connectors	SMA pair	30
	d. MGT REFCLK SMA	SMA pair	30
	connectors
8	GTX RX/TX port	SMA x4	30
9	PCIe Gen1 (8-lane),	Card edge connector, 8-lane	21
	Gen2 (4-lane)
10	SFP connector and cage	AMP 136073-1	23
11	Ethernet (10/100/1000) with	Marvell M88E1111 EPHY	24
	SGMII
12	USB Mini-B, USB-to-UART	Silicon Labs CP2103GM bridge	33
	bridge
13	USB-A Host, USB Mini-B	Cypress CY7C67300-100AXI	27
	peripheral connectors	controller
14	Video - DVI connector	Chrontel CH7301C-TF Video codec	28, 29
15	IIC NV EEPROM, 8 Kb	ST Microelectronics M24C08-	32
	(on backside)	WDW6TP
	Status LEDs		13, 24, 31
	a. Ethernet status	Right-angle link rate and direction	24
16		LEDs
	b. FPGA INIT, DONE	Init (red), Done (green)	31
	c. System ACE CF status	Status (green), Error (red)	13
	User I/O		31
	a. User LEDs, green (8)	User I/O (active-High)	30, 31, 33
	b. User pushbuttons, N.O.	User I/O (active-High)	31
	momentary (5)
17	c. User LEDs, green (5)	User I/O (active-High)	31
	d. User DIP switch (8-pole)	User I/O (active-High)	31
	e. User GPIO SMA	SMA pair	30
	connectors
	f. LCD 16 character x 2 line	Displaytech S162D BA BC	33
	display

12	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010