FLASHD0 DQ0, FLASHD1 DQ1, FLASHD2 DQ2, FLASHD3 DQ3 | Xilinx ML605

Chapter 1: ML605 Evaluation Board

Table 1-5:Platform Flash and BPI Flash Connections (Cont’d)

	U1 FPGA Pin	Schematic Net Name	U4 BPI Flash		U27 Platform Flash

			Pin Number	Pin Name	Pin Number	Pin Name
			Pin Number	Pin Name	Pin Number	Pin Name


	AF24	FLASH_D0	34	DQ0	F2	DQ00

	AF25	FLASH_D1	36	DQ1	E2	DQ01

	W24	FLASH_D2	39	DQ2	G3	DQ02

	V24	FLASH_D3	41	DQ3	E4	DQ03

	H24	FLASH_D4	47	DQ4	E5	DQ04

	H25	FLASH_D5	49	DQ5	G5	DQ05

	P24	FLASH_D6	51	DQ6	G6	DQ06

	R24	FLASH_D7	53	DQ7	H7	DQ07

	G23	FLASH_D8	35	DQ8	E1	DQ08

	H23	FLASH_D9	37	DQ9	E3	DQ09

	N24	FLASH_D10	40	DQ10	F3	DQ10

	N23	FLASH_D11	42	DQ11	F4	DQ11

	F23	FLASH_D12	48	DQ12	F5	DQ12

	F24	FLASH_D13	50	DQ13	H5	DQ13

	L24	FLASH_D14	52	DQ14	G7	DQ14

	M23	FLASH_D15	54	DQ15	E7	DQ15


	J26	FLASH_WAIT	56	WAIT	NA(1)	NA(1)
	AF23	FPGA_FWE_B	14	/WE	G8	/W

	AA24	FPGA_FOE_B	32	/OE	F8	/G

	K8	FPGA_CCLK	NA(1)	NA(1)	F1	K
	AC23	PLATFLASH_L_B	NA(1)	NA(1)	H1	/L
	Y24	FPGA_FCS_B(2)	NA(1)	NA(1)	NA(1)	NA(1)
	NA(1)	PLATFLASH_FCS_B(3)	NA(1)	NA(1)	B4	/E
	NA(1)	FLASH_CE_B(4)	30	/OE	NA(1)	NA(1)

Notes:

1.Not Applicable

2.FPGA control flash memory select signal connected to pin U10.3

3.Platform Flash select signal connected to pin U10.6

4.BPI Flash select signal connected to pin U10.4

22	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 22

Xilinx ML605 manual FLASHD0 DQ0, FLASHD1 DQ1, FLASHD2 DQ2, FLASHD3 DQ3, FLASHD4 DQ4, FLASHD5 DQ5, FLASHD6 DQ6, FLASHD7 DQ7

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information SMA FeaturesML605 Evaluation Board IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram Detailed Description ML605 FeaturesFeature DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga Cclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga Bank VCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6 SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit0 13Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111 PHYRXD5 PHYRXD4RXD4 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs Controlled LED User I/OFpga Init and Done LEDs Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch Pin Usersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators Vccaux UCD9240PFCVccintfpga UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References