8PCIe Edge Connector Connections | Xilinx ML605 specs

Detailed Description

Table 1-8shows the PCIe connector (P1) that provides up to 8-lane access through the GTX transceivers to the Virtex-6 FPGA integrated Endpoint block for PCIe designs.

Table 1-8:PCIe Edge Connector Connections

	U1 FPGA	Schematic Net Name	P1 PCIe Edge Connector		Description	Package
	U1 FPGA					Package
	Pin		Pin Number	Pin Name		Placement
	Pin					Placement


	F1	PCIE_TXO_P	A16	PERp0	Integrated Endpoint block	GTXE1_X0Y15
					Integrated Endpoint block
	F2	PCIE_TXO_N	A17	PERn0	transmit pair
					transmit pair


	H1	PCIE_TX1_P	A21	PERp1	Integrated Endpoint block	GTXE1_X0Y14
					Integrated Endpoint block
	H2	PCIE_TX1_N	A22	PERn1	transmit pair
					transmit pair


	K1	PCIE_TX2_P	A25	PERp2	Integrated Endpoint block	GTXE1_X0Y13
					Integrated Endpoint block
	K2	PCIE_TX2_N	A26	PERn2	transmit pair
					transmit pair


	M1	PCIE_TX3_P	A29	PERp3	Integrated Endpoint block	GTXE1_X0Y11
					Integrated Endpoint block
	M2	PCIE_TX3_N	A30	PERn3	transmit pair
					transmit pair


	P1	PCIE_TX4_P	A35	PERp4	Integrated Endpoint block	GTXE1_X0Y10
					Integrated Endpoint block
	P2	PCIE_TX4_N	A36	PERn4	transmit pair
					transmit pair


	T1	PCIE_TX5_P	A39	PERp5	Integrated Endpoint block	GTXE1_X0Y9
					Integrated Endpoint block
	T2	PCIE_TX5_N	A40	PERn5	transmit pair
					transmit pair


	V1	PCIE_TX6_P	A43	PERp6	Integrated Endpoint block	GTXE1_X0Y8
					Integrated Endpoint block
	V2	PCIE_TX6_N	A44	PERn6	transmit pair
					transmit pair


	Y1	PCIE_TX7_P	A47	PERp7	Integrated Endpoint block	GTXE1_X0Y7
					Integrated Endpoint block
	Y2	PCIE_TX7_N	A48	PERn7	transmit pair
					transmit pair


	J3	PCIE_RXO_P	B14	PETp0	Integrated Endpoint block	GTXE1_X0Y15
					Integrated Endpoint block
	J4	PCIE_RXO_N	B15	PETn0	receive pair
					receive pair


	K5	PCIE_RX1_P	B19	PETp1	Integrated Endpoint block	GTXE1_X0Y14
					Integrated Endpoint block
	K6	PCIE_RX1_N	B20	PETn1	receive pair
					receive pair


	L3	PCIE_RX2_P	B23	PETp2	Integrated Endpoint block	GTXE1_X0Y13
					Integrated Endpoint block
	L4	PCIE_RX2_N	B24	PETn2	receive pair
					receive pair


	N3	PCIE_RX3_P	B27	PETp3	Integrated Endpoint block	GTXE1_X0Y11
					Integrated Endpoint block
	N4	PCIE_RX3_N	B28	PETn3	receive pair
					receive pair


	R3	PCIE_RX4_P	B33	PETp4	Integrated Endpoint block	GTXE1_X0Y10
					Integrated Endpoint block
	R4	PCIE_RX4_N	B34	PETn4	receive pair
					receive pair


	U3	PCIE_RX5_P	B37	PETp5	Integrated Endpoint block	GTXE1_X0Y9
					Integrated Endpoint block
	U4	PCIE_RX5_N	B38	PETn5	receive pair
					receive pair


	W3	PCIE_RX6_P	B41	PETp6	Integrated Endpoint block	GTXE1_X0Y8
					Integrated Endpoint block
	W4	PCIE_RX6_N	B42	PETn6	receive pair
					receive pair

ML605 Hardware User Guide	www.xilinx.com	33
UG534 (v1.2.1) January 21, 2010

Image 33

Xilinx ML605 manual 8PCIe Edge Connector Connections

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm ML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential SMA Pin SmarefclknSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs User Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED Switch Pin User DIP Switch User SMA Gpio UsersmagpionUsersmagpiop J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections Power Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References