11 /100/1000 Tri-Speed Ethernet PHY, Bit2 Bit1 Bit0 | Xilinx ML605

Chapter 1: ML605 Evaluation Board

Table 1-10:SFP Module Connections

	U1 FPGA Pin	Schematic Net Name	P4 SFP Module Connector

			Pin Number	Pin Name
			Pin Number	Pin Name

	E3	SFP_RX_P	13	RDP_13

	E4	SFP_RX_N	12	RDN_12

	C3	SFP_TX_P	18	TDP_18

	C4	SFP_TX_N	19	TDN_19

	V23	SFP_LOS	8	LOS

	AP12	SFP_TX_DISABLE(1)	3	TX_DISABLE

Notes:

1.The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is driven by the FPGA signal SFP_TX_DISABLE_FPGA.

11.10/100/1000 Tri-Speed Ethernet PHY

The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII interfaces from the FPGA to the PHY (Table 1-11). The PHY connection to a user- provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.

Table 1-11:PHY Default Interface Mode

	Mode		Jumper Settings

		J66	J67	J68
		J66	J67	J68

	GMII/MII to copper	Jumper over pins 1-2	Jumper over pins 1-2	No jumper
	(default)	Jumper over pins 1-2	Jumper over pins 1-2	No jumper
	(default)

	SGMII to copper,	Jumper over pins 2-3	Jumper over pins 2-3	No jumper
	no clock	Jumper over pins 2-3	Jumper over pins 2-3	No jumper
	no clock

	RGMII	Jumper over pins 1-2	No jumper	Jumper on

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-12. These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-12:Board Connections for PHY Configuration Pins

	Pin	Connection on	Bit[2]	Bit[1]	Bit[0]
	Pin	Board	Definition and Value	Definition and Value	Definition and Value
		Board	Definition and Value	Definition and Value	Definition and Value

	CFG0	VCC 2.5V	PHYADR[2] = 1	PHYADR[1] = 1	PHYADR[0] = 1
	CFG1	Ground	ENA_PAUSE = 0	PHYADR[4] = 0	PHYADR[3] = 0

	CFG2	VCC 2.5V	ANEG[3] = 1	ANEG[2] = 1	ANEG[1] = 1
	CFG3	VCC 2.5V	ANEG[0] = 1	ENA_XC = 1	DIS_125 = 1
	CFG4	VCC 2.5V	HWCFG_MD[2] = 1	HWCFG_MD[1] = 1	HWCFG_MD[0] = 1

36			www.xilinx.com	ML605 Hardware User Guide
				UG534 (v1.2.1) January 21, 2010

Image 36

Xilinx ML605 11 /100/1000 Tri-Speed Ethernet PHY, 11PHY Default Interface Mode Jumper Settings J66 J67 J68, Bit2 Bit1 Bit0

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information Features ML605 Evaluation BoardSMA IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram ML605 Features FeatureDetailed Description DDR3 Sodimm ML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga 2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga Bank MB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers SMA Pin SmarefclknSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 12Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 PHYRXD4 RXD4PHYRXD5 RXD5 USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs User I/O Fpga Init and Done LEDsControlled LED Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs User Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED User DIP Switch Switch Pin User SMA Gpio UsersmagpionUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin Power Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators UCD9240PFC VccintfpgaVccaux UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References