Xilinx ML605 instruction

Detailed Description

Table 1-28:VITA 57.1 FMC HPC Connections (Cont’d)

J64 FMC	Schematic Net Name	U1 FPGA		J64 FMC	Schematic Net Name	U1 FPGA
HPC Pin	Schematic Net Name	Pin		HPC Pin	Schematic Net Name	Pin
HPC Pin		Pin		HPC Pin		Pin


J2	FMC_HPC_CLK3_M2C_P(2)	U84.6		K4	FMC_HPC_CLK2_M2C_P(2)	U83.6
J3	FMC_HPC_CLK3_M2C_N(2)	U84.7		K5	FMC_HPC_CLK2_M2C_N(2)	U83.7
J6	FMC_HPC_HA03_P	AA25		K7	FMC_HPC_HA02_P	AB25

J7	FMC_HPC_HA03_N	Y26		K8	FMC_HPC_HA02_N	AC25

J9	FMC_HPC_HA07_P	AA26		K10	FMC_HPC_HA06_P	AA28

J10	FMC_HPC_HA07_N	AB26		K11	FMC_HPC_HA06_N	AA29

J12	FMC_HPC_HA11_P	AG33		K13	FMC_HPC_HA10_P	AD34

J13	FMC_HPC_HA11_N	AG32		K14	FMC_HPC_HA10_N	AC34

J15	FMC_HPC_HA14_P	AA30		K16	FMC_HPC_HA17_CC_P	V30

J16	FMC_HPC_HA14_N	AA31		K17	FMC_HPC_HA17_CC_N	W30

J18	FMC_HPC_HA18_P	T33		K19	FMC_HPC_HA21_P	U31

J19	FMC_HPC_HA18_N	T34		K20	FMC_HPC_HA21_N	U30

J21	FMC_HPC_HA22_P	U28		K22	FMC_HPC_HA23_P	U26

J22	FMC_HPC_HA22_N	V29		K23	FMC_HPC_HA23_N	U27

J24	FMC_HPC_HB01_P	AN32		K25	FMC_HPC_HB00_CC_P	AF30

J25	FMC_HPC_HB01_N	AM32		K26	FMC_HPC_HB00_CC_N	AG30

J27	FMC_HPC_HB07_P	AJ34		K28	FMC_HPC_HB06_CC_P	AF26

J28	FMC_HPC_HB07_N	AH34		K29	FMC_HPC_HB06_CC_N	AE26

J30	FMC_HPC_HB11_P	AJ29		K31	FMC_HPC_HB10_P	AF28

J31	FMC_HPC_HB11_N	AJ30		K32	FMC_HPC_HB10_N	AF29

J33	FMC_HPC_HB15_P	AE28		K34	FMC_HPC_HB14_P	AE27

J34	FMC_HPC_HB15_N	AE29		K35	FMC_HPC_HB14_N	AD27

J36	FMC_HPC_HB18_P	AD25		K37	FMC_HPC_HB17_CC_P	AG27

J37	FMC_HPC_HB18_N	AD26		K38	FMC_HPC_HB17_CC_N	AG28

Notes:

1.Signals ending with _LS are not directly connected to the FMC HPC connector. _LS signals are connected between the listed U1 FPGA pin and a level shifter device. The signal connected between the shifted side of said device and the FMC HPC pin listed has the same signal name, without the _LS on the end.

2.These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals are connected to (U88.17 = U88 pin 17, and so on).

ML605 Hardware User Guide	www.xilinx.com	61
UG534 (v1.2.1) January 21, 2010

Image 61

Xilinx ML605 manual Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential Smarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP Switch Usersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References