Detailed Description

System Monitor Header (J35)

Figure 1-30shows the pinout for the System Monitor 12-pin header. The header provides user access to the analog power supply (AVdd) and the 1.25V reference shown in Figure 1-29, page 68. Access to the FPGA thermal diode and dedicated analog input channel (Vp/Vn) is also provided on this header. The header can be used to connect user specific analog signals and sensors to the system monitor.

The kelvin points for a 5 milliohm current sensing shunt in the FPGA 1V Vccint core supply are also available on this header. By connecting header pins 9 to 11 and 10 to 12 using

jumpers, the system monitor can be used to monitor the FPGA core current and power consumption. This can be used to collect useful power information about a particular design or implementation.

Anti-alias Filter

SYSMON_VN

R232

100 1%

1/16W

 

 

 

C169

R233

100 1%

1/16W

16V

X7R

 

 

 

SYSMON_VP

0.01UF

Dedicated Analog Inputs

 

 

System Monitor

 

 

FPGA

 

 

 

 

Thermal Diode

 

 

Header J35

 

 

 

 

 

 

access

 

 

 

 

NC

1

2

 

FPGA_DX_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

3

4

 

FPGA_DX_N

 

 

 

 

 

 

5

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.25V Reference

 

7

8

 

SYSMON_AVDD

 

 

 

 

 

 

 

 

 

 

 

9

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vccint_shunt_N

 

11

12

 

Vccint_shunt_P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AGND

To Measure VCCINT Current:

Jumper on 9-11, 10-12

Connect Vccint shunt to Vp,Vn

UG534_37 _081209

Figure 1-30:System Monitor Header (J35)

ML605 Hardware User Guide

www.xilinx.com

69

UG534 (v1.2.1) January 21, 2010

 

 

Page 69
Image 69
Xilinx ML605 manual System Monitor Header J35