USB Jtag | Xilinx ML605 instruction

Chapter 1: ML605 Evaluation Board

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (ML605 side) USB cable.

The JTAG chain of the board is illustrated in Figure 1-4. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.

J22

USB Mini-B

FMC HPC

TDI TDO

J64

J17

FMC LPC

TDI TDO

J63

J18

3.3V

2.5V

System ACE CF

FPGA

TSTTDI

CFGTDO

TDI

U19

U1

TSTTDO

CFGTDI

TDO

UG534_04_081309

Figure 1-4:JTAG Chain Diagram

FMC bypass jumpers J17 and J18 must be connected between pins 1-2 (bypass) to enable JTAG access to the FPGA on the basic ML605 board (without FMC expansion modules installed), as shown in Figure 1-5and Figure 1-6. When either or both VITA 57.1 FMC expansion connectors are populated with an expansion module that has a JTAG chain, the respective jumper(s) must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG chain in the main ML605 JTAG chain.

J17

1

FMC_TDI_BUF

2

FMC_LPC_TDI

3

FMC_HPC_TDO

Bypass FMC HPC J64 = Jumper 1-2

Include FMC HPC J64 = Jumper 2-3

H - 1x3

UG534_05_081309

Figure 1-5:VITA 57.1 FMC HPC (J64) JTAG Bypass Jumper J17

J18

1

FMC_LPC_TDI

2

SYSACE_TDI

3

FMC_LPC_TDO

Bypass FMC LPC J63 = Jumper 1-2

Include FMC LPC J63 = Jumper 2-3

H - 1x3

UG534_06_081309

Figure 1-6:VITA 57.1 FMC LPC (J63) JTAG Bypass Jumper J18

26	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 26

Xilinx ML605 manual USB Jtag

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information SMA FeaturesML605 Evaluation Board IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram Detailed Description ML605 FeaturesFeature DDR3 Sodimm WDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga Cclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga Bank VCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkp SMA PinSmarefclkn Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6 SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit0 13Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111 PHYRXD5 PHYRXD4RXD4 RXD5 Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs Controlled LED User I/OFpga Init and Done LEDs Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Gpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin User DIP Switch Switch Pin Usersmagpiop User SMA GpioUsersmagpion LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin Detailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch Onboard Power Regulation 28ML605 Onboard Power Regulators Vccaux UCD9240PFCVccintfpga UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References