LCD Display 16 Character x 2 Lines, J41 Pin | Xilinx ML605 specification

Chapter 1: ML605 Evaluation Board

LCD_DB7

LCD_DB5

LCD_E

LCD_RS

52

LCD Display (16 Character x 2 Lines)

The ML605 board has a 16-character x 2-line LCD (Display Tech S162D BA BC, installed onto J41 2x7 header) on the board to display text information. Potentiometer R270 adjusts the contrast of the LCD. A ST2378E (U33) 2.5V-to-5V level-shifter is used to shift the voltage level between the FPGA and the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. The LCD module has a connector that allows the LCD to be removed from the board to access to the components below it.

Caution! Care should be taken not to scratch or damage the surface of the LCD window.

VCC5

											VCC5
					J41																	R158
					J41															1		2
			1								2			LCD_DB6					32	1		2
																						6.81K	1%

			3								4			LCD_DB4					32	1



NC			5								6			NC


NC			7								8			NC					32			R270


			9								10			LCD_RW								0-2K


			11								12			LCD_VEE						2		1/2W



																						20%
			13								14											20%
																						silkscreen:



				SSW-107-01-T-D																3
				SSW-107-01-T-D																3		“LCD Contrast”
																						“LCD Contrast”
																						UG534_22_073109
			Figure 1-22:LCD Header J41 and Contrast Trimpot R270
		Table 1-25:LCD Header Connections

		U1 FPGA Pin						Schematic Net Name								J41 Pin

				AD14							LCD_DB4_LS					4

				AK11							LCD_DB5_LS					3

				AJ11							LCD_DB6_LS					2

				AE12							LCD_DB7_LS					1

				AC14							LCD_RW_LS					10

				T28							LCD_RS_LS					11

				AK12							LCD_E_LS					9

www.xilinx.com	ML605 Hardware User Guide
	UG534 (v1.2.1) January 21, 2010

Image 52

Xilinx ML605 manual LCD Display 16 Character x 2 Lines, J41 Pin

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information Features ML605 Evaluation BoardSMA IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram ML605 Features FeatureDetailed Description DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga 2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga Bank MB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 12Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 PHYRXD4 RXD4PHYRXD5 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs User I/O Fpga Init and Done LEDsControlled LED Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch Pin Usersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators UCD9240PFC VccintfpgaVccaux UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References