28VITA 57.1 FMC HPC Connections, HPC Pin | Xilinx ML605 specs

Chapter 1: ML605 Evaluation Board

Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

Table 1-28shows the VITA 57.1 FMC HPC connections. The connector pinout is in

Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout.”

Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table.

Table 1-28:VITA 57.1 FMC HPC Connections

J64 FMC	Schematic Net Name	U1 FPGA		J64 FMC	Schematic Net Name	U1 FPGA
HPC Pin	Schematic Net Name	Pin		HPC Pin	Schematic Net Name	Pin
HPC Pin		Pin		HPC Pin		Pin

A2	FMC_HPC_DP1_M2C_P	AE3		B12	FMC_HPC_DP7_M2C_P	AP5

A3	FMC_HPC_DP1_M2C_N	AE4		B13	FMC_HPC_DP7_M2C_N	AP6

A6	FMC_HPC_DP2_M2C_P	AF5		B16	FMC_HPC_DP6_M2C_P	AM5

A7	FMC_HPC_DP2_M2C_N	AF6		B17	FMC_HPC_DP6_M2C_N	AM6

A10	FMC_HPC_DP3_M2C_P	AG3		B20	FMC_HPC_GBTCLK1_M2C_P	AK6

A11	FMC_HPC_DP3_M2C_N	AG4		B21	FMC_HPC_GBTCLK1_M2C_N	AK5

A14	FMC_HPC_DP4_M2C_P	AJ3		B32	FMC_HPC_DP7_C2M_P	AP1

A15	FMC_HPC_DP4_M2C_N	AJ4		B33	FMC_HPC_DP7_C2M_N	AP2

A18	FMC_HPC_DP5_M2C_P	AL3		B36	FMC_HPC_DP6_C2M_P	AN3

A19	FMC_HPC_DP5_M2C_N	AL4		B37	FMC_HPC_DP6_C2M_N	AN4

A22	FMC_HPC_DP1_C2M_P	AD1

A23	FMC_HPC_DP1_C2M_N	AD2

A26	FMC_HPC_DP2_C2M_P	AF1

A27	FMC_HPC_DP2_C2M_N	AF2

A30	FMC_HPC_DP3_C2M_P	AH1

A31	FMC_HPC_DP3_C2M_N	AH2

A34	FMC_HPC_DP4_C2M_P	AK1

A35	FMC_HPC_DP4_C2M_N	AK2

A38	FMC_HPC_DP5_C2M_P	AM1

A39	FMC_HPC_DP5_C2M_N	AM2


C2	FMC_HPC_DP0_C2M_P	AB1		D4	FMC_HPC_GBTCLK0_M2C_P	AD6

C3	FMC_HPC_DP0_C2M_N	AB2		D5	FMC_HPC_GBTCLK0_M2C_N	AD5

C6	FMC_HPC_DP0_M2C_P	AC3		D8	FMC_HPC_LA01_CC_P	AK19

C7	FMC_HPC_DP0_M2C_N	AC4		D9	FMC_HPC_LA01_CC_N	AL19

C10	FMC_HPC_LA06_P	AG20		D11	FMC_HPC_LA05_P	AG22

C11	FMC_HPC_LA06_N	AG21		D12	FMC_HPC_LA05_N	AH22

58	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010

Image 58

Xilinx ML605 manual 28VITA 57.1 FMC HPC Connections, HPC Pin

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information SMA FeaturesML605 Evaluation Board IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram Detailed Description ML605 FeaturesFeature DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga Cclk Direction 2Virtex-6 Fpga Configuration Modes M20Voltage Rails 3Voltage Rails U1 Fpga Bank VCC1V5FPGA MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD2 DQ2 FLASHD0 DQ0FLASHD1 DQ1 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections PCIE100MMGT0P AA3 PCIERX7PAA4 PCIERX7N GTXE1X0Y6 SFP Module Connector 11 /100/1000 Tri-Speed Ethernet PHY 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins Bit2 Bit1 Bit0 13Ethernet PHYConnections U1 Fpga Pin 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation U80 M88E1111 PHYRXD5 PHYRXD4RXD4 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs Controlled LED User I/OFpga Init and Done LEDs Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch Pin Usersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB13P FMCHPCHB09NFMCHPCHB08P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFAM2C Vadj VadjVIOBM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators Vccaux UCD9240PFCVccintfpga UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References