28VITA 57.1 FMC HPC Connections Cont’d | Xilinx ML605 guide

								Detailed Description

Table 1-28:VITA 57.1 FMC HPC Connections (Cont’d)

J64 FMC			Schematic Net Name	U1 FPGA			J64 FMC	Schematic Net Name	U1 FPGA
HPC Pin			Schematic Net Name	Pin			HPC Pin	Schematic Net Name	Pin
HPC Pin				Pin			HPC Pin		Pin

C14			FMC_HPC_LA10_P	AM20			D14	FMC_HPC_LA09_P	AM18

C15			FMC_HPC_LA10_N	AL20			D15	FMC_HPC_LA09_N	AL18

C18			FMC_HPC_LA14_P	AN19			D17	FMC_HPC_LA13_P	AP19

C19			FMC_HPC_LA14_N	AN20			D18	FMC_HPC_LA13_N	AN18

C22			FMC_HPC_LA18_CC_P	AH25			D20	FMC_HPC_LA17_CC_P	AN27

C23			FMC_HPC_LA18_CC_N	AJ25			D21	FMC_HPC_LA17_CC_N	AM27

C26			FMC_HPC_LA27_P	AP30			D23	FMC_HPC_LA23_P	AL26

C27			FMC_HPC_LA27_N	AP31			D24	FMC_HPC_LA23_N	AM26

C30			IIC_SCL_MAIN_LS(1)	AK9			D26	FMC_HPC_LA26_P	AM25
C31			IIC_SDA_MAIN_LS(1)	AE9			D27	FMC_HPC_LA26_N	AL25
							D29	FMC_HPC_TCK_BUF(2)	U88.15
							D30	FMC_TDI_BUF(2)	J17.1
							D31	FMC_HPC_TDO(2)	J17.3
							D33	FMC_TMS_BUF(2)	U88.17

E2			FMC_HPC_HA01_CC_P	AD29			F1	FMC_HPC_PG_M2C_LS(1)	J27
E3			FMC_HPC_HA01_CC_N	AC29			F4	FMC_HPC_HA00_CC_P	AE33

E6			FMC_HPC_HA05_P	AB27			F5	FMC_HPC_HA00_CC_N	AF33

E7			FMC_HPC_HA05_N	AC27			F7	FMC_HPC_HA04_P	AB28

E9			FMC_HPC_HA09_P	AB30			F8	FMC_HPC_HA04_N	AC28

E10			FMC_HPC_HA09_N	AB31			F10	FMC_HPC_HA08_P	AG31

E12			FMC_HPC_HA13_P	AE31			F11	FMC_HPC_HA08_N	AF31

E13			FMC_HPC_HA13_N	AD31			F13	FMC_HPC_HA12_P	AD32

E15			FMC_HPC_HA16_P	AC33			F14	FMC_HPC_HA12_N	AE32

E16			FMC_HPC_HA16_N	AB33			F16	FMC_HPC_HA15_P	AB32

E18			FMC_HPC_HA20_P	V32			F17	FMC_HPC_HA15_N	AC32

E19			FMC_HPC_HA20_N	V33			F19	FMC_HPC_HA19_P	U33

E21			FMC_HPC_HB03_P	AL30			F20	FMC_HPC_HA19_N	U32

E22			FMC_HPC_HB03_N	AM31			F22	FMC_HPC_HB02_P	AP32

E24			FMC_HPC_HB05_P	AN33			F23	FMC_HPC_HB02_N	AP33

E25			FMC_HPC_HB05_N	AN34			F25	FMC_HPC_HB04_P	AM33

E27			FMC_HPC_HB09_P	AL34			F26	FMC_HPC_HB04_N	AL33

ML605 Hardware User Guide	www.xilinx.com	59
UG534 (v1.2.1) January 21, 2010

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Xilinx ML605 manual 28VITA 57.1 FMC HPC Connections Cont’d

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board IIC Eeprom 1 KB FeaturesML605 Evaluation Board SMA Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram DDR3 Sodimm ML605 FeaturesFeature Detailed Description WDW6TP ML605 Evaluation Board ML605 Features Cont’dSgmii Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration 3Voltage Rails U1 Fpga Bank 2Virtex-6 Fpga Configuration Modes M20Voltage Rails Cclk Direction 4DDR3 Sodimm Connections MB DDR3 Memory SodimmDetailed Description 3Voltage Rails Cont’d U1 Fpga Bank VCC1V5FPGA DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD3 DQ3 FLASHD0 DQ0FLASHD1 DQ1 FLASHD2 DQ2 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Socket Single-Ended Clock GenerationOscillator Differential 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential Smarefclkp SMA PinSmarefclkn ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections GTXE1X0Y6 AA3 PCIERX7PAA4 PCIERX7N PCIE100MMGT0P SFP Module Connector Bit2 Bit1 Bit0 11PHY Default Interface Mode Jumper Settings J66 J67 J6812Board Connections for PHY Configuration Pins 11 /100/1000 Tri-Speed Ethernet PHY U80 M88E1111 12Board Connections for PHY Configuration Pins Cont’dSgmii GTX Transceiver Clock Generation 13Ethernet PHYConnections U1 Fpga Pin RXD5 PHYRXD4RXD4 PHYRXD5 Ground USB-to-UART BridgeVbus U81 USB Controller USB Controller16USB Controller Connections U38 Chrontel CH7301C DVI Codec17DVI Controller Connections IIC Bus 14IIC Bus Topology Iicsclmain SCL Kb NV MemoryIicsdamain SDA Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpgainitb User I/OFpga Init and Done LEDs Controlled LED User LEDs 18User LEDs and Gpio Connector, Directional LEDs Gpio J62 Pin Controlled LED User Pushbutton SwitchesDetailed Description 21User LED Connections Fpga U1 Pin Switch Pin User DIP Switch Usersmagpiop User SMA GpioUsersmagpion J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08N FMCHPCHB09NFMCHPCHB08P FMCHPCHB13P Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VREFBM2C VadjVIOBM2C Vadj VREFAM2C Vadj Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections Detailed Description 30VITA 57.1 FMC LPC Connections Cont’d Power ManagementAC Adapter and Input Power Jack/Switch 28ML605 Onboard Power Regulators Onboard Power Regulation UCD7230RGWR UCD9240PFCVccintfpga Vccaux 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References