Xilinx ML605 9. PCI Express Endpoint Connectivity

32 www.xilinx.com ML605 Hardware User Guide

UG534 (v1.2.1) January 21, 2010

Chapter 1: ML605 Evaluation Board

9. PCI Express Endpoint Connectivity

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1

application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for

the multi-gigabit per second serial interfaces.

The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2

applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed

grade for the LX240T device.

Figure1-11, page 32 is a diagram of the PCIe MGT bank 114 and 115 clocking.

PCIe lane width/size is selected via jumper J42 as shown in Figure1-12. The default lane

size selection is 1-lane (J42 pins 1 and 2 jumpered).

X-Ref Target - Figure 1-11

Figure 1-11: PCIe MGT Banks 114 and 115 Clocking

UG534_11_100809

P1

U1

Bank 115

ICS874001

ICS854104

REFCLK+,-

PERp,n[7:0]

PCIE_TX[7:0]_P/N

PCIE_RX[7:0]_P/N

MGTREFCLK0 P/N

PETp,n[7:0]

PCIE_CLK_Q0_P/N

Note: PCIe edge connector signal nomenclature is

from perspective of the system/motherboard.

PCIE_100M_MGT1_P/N

PCIE_100M_MGT0_P/N

PCIE_100M_MGT0_C_P/N PCIE_250M_MGT1_C_P/N

PCIE_250M_MGT1_P/N

CLK/NCLK

PCIe

8-Lane

Edge

Connector

MGTTX

P/N[3:0]

MGTRX

P/N[3:0]

U1

Bank 114

MGTREFCLK0 P/N

MGTTX

P/N[7:4]

MGTRX

P/N[7:4]

U14

Q1/NQ1

Q0/NQ0

CLK/NCLK

U9

Q/NQ

X-Ref Target - Figure 1-12

Figure 1-12: PCIe Lane Size Select Jumper J42

J42

12

34

56

H-2X3

PCIE_PRSNT_B

PCIE_PRSNT_X8

PCIE_PRSNT_X4

PCIE_PRSNT_X1

UG534_12_111709

Contents

Main Revision History The following table shows the revision history for this document. Table of Contents Preface: About This Guide Guide Contents Additional Documentation Additional Support Resources Chapter 1: ML605 Evaluation Board Overview Page Preface About This Guide Guide Contents Additional Documentation Additional Support Resources Chapter 1 ML605 Evaluation Board Overview Additional Information Features Page 10 www.xilinx.com ML605 Hardware User Guide UG534 (v1.2.1) January 21, 2010 Block Diagram Figure1-1 shows a high-level block diagram of the ML605 and its peripherals. Figure 1-1: ML605 High-Level Block Diagram Related Xilinx Documents Detailed Description Figure 1-2: ML605 Board Photo The numbered features in Figure1-2 correlate to the features and notes listed in Ta ble 1- 1. Table 1-1: ML605 Features Table 1-1: ML605 Features (Contd) 1. Virtex-6 XC6VLX240T-1FFG1156 FPGA Configuration I/O Voltage Rails 2. 512 MB DDR3 Memory SODIMM Page Page Page Page 3. 128 Mb Platform Flash XL 4. 32 MB Linear BPI Flash S1 Switch 4 ML605 Flash Boot Options Table 1-5: Platform Flash and BPI Flash Connections (Contd) FPGA Design Considerations for the Configuration Flash 5. System ACE CF and CompactFlash Connector Tabl e 1-6 lists the System ACE CF connections. See the System ACE CF product page and the System ACE CompactFlash Solution Data Sheet. [Ref 18] Table 1-6: System ACE CF Connections 6. USB JTAG 7. Clock Generation Oscillator (Differential) Oscillator Socket (Single-Ended, 2.5V) Page SMA Connectors (Differential) GTX SMA Clock J31 32K10K-400E3 SMA_REFCLK_C_N1 Figure 1-9: GTX SMA Clock J30 32K10K-400E3 8. Multi-Gigabit Transceivers (GTX MGTs) ICS874001 BANK_115BANK_114BANK_113BANK_112 BANK_116 Figure 1-10: MGT Clocking See the Virtex-6 FPGA GTX Transceivers User Guide. [Ref12] 9. PCI Express Endpoint Connectivity Page Page 10. SFP Module Connector 11. 10/100/1000 Tri-Speed Ethernet PHY SGMII GTX Transceiver Clock Generation Figure 1-13: Ethernet SGMII Clock - 125 MHz Tabl e 1-13 shows the connections and pin numbers for the PHY. Table 1-12: Board Connections for PHY Configuration Pins (Contd) Table 1-13: Ethernet PHYConnections Table 1-13: Ethernet PHYConnections (Contd) 12. USB-to-UART Bridge 13. USB Controller 14. DVI Codec 15. IIC Bus Figure 1-14: IIC Bus Topology U1 J63 P3 U38 8 Kb NV Memory FPGA U1 Pin Schematic Net Name Figure 1-15: IIC Memory U6 Table 1-18: IIC Memory Connections 16. Status LEDs Tabl e 1-19 defines the status LEDs. Table 1-19: Status LEDs Ethernet PHY Status LEDs FPGA INIT and DONE LEDs 17. User I/O 48 www.xilinx.com ML605 Hardware User Guide User LEDs The ML605 provides two groups of active-High LEDs as described in Figure1-18 and Tabl e 1-21 . Figure 1-18: User LEDs and GPIO Connector, Directional LEDs Note: User Pushbutton Switches User DIP Switch Figure 1-20: User 8-pole DIP Switch Table 1-22: User Pushbutton Switch Connections U1 FPGA Pin Schematic Net Name Pushbutton Switch Pin Table 1-23: User DIP Switch Connections User SMA GPIO USER SMA GPIO P USER SMA GPIO N Figure 1-21: User SMA GPIO Table 1-24: User SMA Connections LCD Display (16 Character x 2 Lines) 1 Figure 1-22: LCD Header J41 and Contrast Trimpot R270 2 34 56 78 910 11 12 1314 Table 1-25: LCD Header Connections PCIe Power FPGA_PROG_B Pushbutton SW4 (Active-Low) SYSACE_RESET_B Pushbutton SW3 (Active-Low) ML605 Hardware User Guide www.xilinx.com 55 System ACE CF CompactFlash Image Select DIP Switch S1 ON 5 6 7 Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2 R55 R54 R53 R50 19. VITA 57.1 FMC HPC Connector Note: Page Chapter 1: ML605 Evaluation Board Page Page 20. VITA 57.1 FMC LPC Connector Page 21. Power Management AC Adapter and Input Power Jack/Switch Onboard Power Regulation Page 22. System Monitor Reference and Power Supply U23 System Monitor Header (J35) ML605 Board Power Monitor 12V Supply Monitor V Current Channel V Voltage Channel 2m Fan Controller 12V Figure 1-32: ML605 Fan Driver J59 GND Tach 6vlx240tff1156 System Monitor ML605 Demonstration Design BANK 34 Configuration Options Page Appendix A Default Switch and Jumper Settings Tabl e A -1 : Default Switch Settings REFDES Function/Type Default 1 SysAce CFGAddr 0 = 0 off Appendix A: Default Switch and Jumper Settings Tabl e A -2 : Default Jumper Settings Appendix B VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout Figure B-1: FMC LPC Connector Pinout FigureB-1 shows the pinout of the FMC LPC connector. Pins marked NC are not connected. Figure B-2: FMC HPC Connector Pinout Appendix C ML605 Master UCF Page Page Page Page Page Page Page Page Page Page Page Appendix D References