Xilinx ML605 manual PCI Express Endpoint Connectivity, 12PCIe Lane Size Select Jumper J42

Chapter 1: ML605 Evaluation Board

9. PCI Express Endpoint Connectivity

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for the multi-gigabit per second serial interfaces.

The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2 applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed grade for the LX240T device.

Figure 1-11, page 32 is a diagram of the PCIe MGT bank 114 and 115 clocking.

Note: PCIe edge connector signal nomenclature is
from perspective of the system/motherboard.
P1		U14		U9
		Q1/NQ1 PCIE_100M_MGT1_P/N CLK/NCLK Q/NQ
REFCLK+,-	PCIE_CLK_Q0_P/N CLK/NCLK
		Q0/NQ0		ICS874001
	ICS854104
	PCIE_100M_MGT0_C_P/N		PCIE_250M_MGT1_C_P/N
	PCIE_100M_MGT0_P/N		PCIE_250M_MGT1_P/N
PERp,n[7:0]		U1		U1
PETp,n[7:0]	Bank 115		Bank 114
	MGTREFCLK0 P/N		MGTREFCLK0 P/N
PCIe	MGTTX	MGTRX	MGTTX	MGTRX
	P/N[3:0]	P/N[3:0]	P/N[7:4]	P/N[7:4]
8-Lane
Edge		PCIE_TX[7:0]_P/N
Connector
		PCIE_RX[7:0]_P/N
				UG534_11_100809
	Figure 1-11:PCIe MGT Banks 114 and 115 Clocking

PCIe lane width/size is selected via jumper J42 as shown in Figure 1-12. The default lane size selection is 1-lane (J42 pins 1 and 2 jumpered).

		J42
PCIE_PRSNT_X1	1	2
PCIE_PRSNT_X4	3	4

PCIE_PRSNT_B

PCIE_PRSNT_X8

56

H-2X3

UG534_12_111709

Figure 1-12:PCIe Lane Size Select Jumper J42

32	www.xilinx.com	ML605 Hardware User Guide
		UG534 (v1.2.1) January 21, 2010