Xilinx manual Appendix C ML605 Master UCF, NET DDR3D9

Models: ML605

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Appendix C: ML605 Master UCF

NET "DDR3_D8"

LOC = "M13";

## 21

on J1

NET "DDR3_D9"

LOC = "J14";

## 23

on J1

NET "DDR3_D10"

LOC = "B13";

## 33

on J1

NET "DDR3_D11"

LOC = "B12";

## 35

on J1

NET "DDR3_D12"

LOC = "G10";

## 22

on J1

NET "DDR3_D13"

LOC = "M11";

## 24

on J1

NET "DDR3_D14"

LOC = "C12";

## 34

on J1

NET "DDR3_D15"

LOC = "A11";

## 36

on J1

NET "DDR3_D16"

LOC = "G11";

## 39

on J1

NET "DDR3_D17"

LOC = "F11";

## 41

on J1

NET "DDR3_D18"

LOC = "D14";

## 51

on J1

NET "DDR3_D19"

LOC = "C14";

## 53

on J1

NET "DDR3_D20"

LOC = "G12";

## 40

on J1

NET "DDR3_D21"

LOC = "G13";

## 42

on J1

NET "DDR3_D22"

LOC = "F14";

## 50

on J1

NET "DDR3_D23"

LOC = "H14";

## 52

on J1

NET "DDR3_D24"

LOC = "C19";

## 57

on J1

NET "DDR3_D25"

LOC = "G20";

## 59

on J1

NET "DDR3_D26"

LOC = "E19";

## 67

on J1

NET "DDR3_D27"

LOC = "F20";

## 69

on J1

NET "DDR3_D28"

LOC = "A20";

## 56

on J1

NET "DDR3_D29"

LOC = "A21";

## 58

on J1

NET "DDR3_D30"

LOC = "E22";

## 68

on J1

NET "DDR3_D31"

LOC = "E23";

## 70

on J1

NET "DDR3_D32"

LOC = "G21";

## 129 on J1

NET "DDR3_D33"

LOC = "B21";

## 131 on J1

NET "DDR3_D34"

LOC = "A23";

## 141 on J1

NET "DDR3_D35"

LOC = "A24";

## 143 on J1

NET "DDR3_D36"

LOC = "C20";

## 130 on J1

NET "DDR3_D37"

LOC = "D20";

## 132 on J1

NET "DDR3_D38"

LOC = "J20";

## 140 on J1

NET "DDR3_D39"

LOC = "G22";

## 142 on J1

NET "DDR3_D40"

LOC = "D26";

## 147 on J1

NET "DDR3_D41"

LOC = "F26";

## 149 on J1

NET "DDR3_D42"

LOC = "B26";

## 157 on J1

NET "DDR3_D43"

LOC = "E26";

## 159 on J1

NET "DDR3_D44"

LOC = "C24";

## 146 on J1

NET "DDR3_D45"

LOC = "D25";

## 148 on J1

NET "DDR3_D46"

LOC = "D27";

## 158 on J1

NET "DDR3_D47"

LOC = "C25";

## 160 on J1

NET "DDR3_D48"

LOC = "C27";

## 163 on J1

NET "DDR3_D49"

LOC = "B28";

## 165 on J1

NET "DDR3_D50"

LOC = "D29";

## 175 on J1

NET "DDR3_D51"

LOC = "B27";

## 177 on J1

NET "DDR3_D52"

LOC = "G27";

## 164 on J1

NET "DDR3_D53"

LOC = "A28";

## 166 on J1

NET "DDR3_D54"

LOC = "E24";

## 174 on J1

NET "DDR3_D55"

LOC = "G25";

## 176 on J1

NET "DDR3_D56"

LOC = "F28";

## 181 on J1

NET "DDR3_D57"

LOC = "B31";

## 183 on J1

NET "DDR3_D58"

LOC = "H29";

## 191 on J1

NET "DDR3_D59"

LOC = "H28";

## 193 on J1

NET "DDR3_D60"

LOC = "B30";

## 180 on J1

NET "DDR3_D61"

LOC = "A30";

## 182 on J1

NET "DDR3_D62"

LOC = "E29";

## 192 on J1

NET "DDR3_D63"

LOC = "F29";

## 194

on J1

NET "DDR3_DM0"

LOC = "E11";

## 11

on J1

NET "DDR3_DM1"

LOC = "B11";

## 28

on J1

NET "DDR3_DM2"

LOC = "E14";

## 46

on J1

NET "DDR3_DM3"

LOC = "D19";

## 63

on J1

NET "DDR3_DM4"

LOC = "B22";

## 136 on J1

NET "DDR3_DM5"

LOC = "A26";

## 153 on J1

NET "DDR3_DM6"

LOC = "A29";

## 170 on J1

NET "DDR3_DM7"

LOC = "A31";

## 187

on J1

NET "DDR3_DQS0_N"

LOC = "E12";

## 10

on J1

80

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ML605 Hardware User Guide

 

 

UG534 (v1.2.1) January 21, 2010

Page 80
Image 80
Xilinx manual Appendix C ML605 Master UCF, NET DDR3D9