Vita 57.1 FMC HPC Connector, Master BPI | Xilinx ML605 specification

Detailed Description

Table 1-27:Switch S2 Configuration Details

		Switch		Configuration Mode/Method

	Switch	Net Name	JTAG		Slave SelectMAP	Master BPI
	Switch	Net Name	System ACE CF		Platform Flash XL	P30 Linear Flash
			System ACE CF		Platform Flash XL	P30 Linear Flash

	S2.1	CCLK_EXTERNAL	Off		On	Off

	S2.2	P30_CS_SEL	On(1)		Off	On
	S2.3	FPGA_M0	On		Off	Off

	S2.4	FPGA_M1	Off		On	On

	S2.5	FPGA_M2	On		On	Off

	S2.6	FLASH_A23	Off		Don't Care	Off(2)

Notes:

1.In JTAG mode, S2.2 is shown as ON for FPGA access to the P30 Linear Flash. Alternatively, set S2.2 to OFF for FPGA access to the Platform Flash XL.

2.In Master BPI mode, S2.6 is shown as OFF for selecting initial configuration from BPI address 0x000000. Alternatively, set S2.6 to ON to select initial configuration from BPI address 0x800000.

See “3. 128 Mb Platform Flash XL,” page 20 and “4. 32 MB Linear BPI Flash,” page 20 for details.

19. VITA 57.1 FMC HPC Connector

The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC HPC J64 connector.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC HPC connector provides connectivity for:

•160 single-ended or 80 differential user-defined signals

•10 MGTs

•2 MGT clocks

•4 differential clocks

•159 ground, 15 power connections

Of the above signal and clock connectivity capability, the ML605 implements the following subset:

•78 differential user defined pairs:

♦34 LA pairs

♦24 HA pairs

♦20 HB pairs

•8 MGTs

•2 MGT clocks

•4 differential clocks

ML605 Hardware User Guide	www.xilinx.com	57
UG534 (v1.2.1) January 21, 2010

Image 57

Xilinx ML605 manual Vita 57.1 FMC HPC Connector, Master BPI

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm ML605 Evaluation Board ML605 Features Cont’d SgmiiWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Clock Generation Oscillator DifferentialOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential SMA Pin SmarefclknSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 USB-to-UART Bridge VbusGround USB Controller 16USB Controller ConnectionsU81 USB Controller DVI Codec 17DVI Controller ConnectionsU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Kb NV Memory Iicsdamain SDAIicsclmain SCL Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs User Pushbutton Switches Detailed Description 21User LED Connections Fpga U1 PinGpio J62 Pin Controlled LED Switch Pin User DIP Switch User SMA Gpio UsersmagpionUsersmagpiop J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections Power Management AC Adapter and Input Power Jack/SwitchDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References