Xilinx ML605 manual

Detailed Description

Table 1-6lists the System ACE CF connections.

Table 1-6:System ACE CF Connections

	U1 FPGA Pin	Schematic Net Name	U19 XCCACETQ144I

			Pin Number	Pin Name
			Pin Number	Pin Name

	AM15	SYSACE_D0	66	MPD00

	AJ17	SYSACE_D1	65	MPD01

	AJ16	SYSACE_D2	63	MPD02

	AP16	SYSACE_D3	62	MPD03

	AG16	SYSACE_D4	61	MPD04

	AH15	SYSACE_D5	60	MPD05

	AF16	SYSACE_D6	59	MPD06

	AN15	SYSACE_D7	58	MPD07

	AC15	SYSACE_MPA00	70	MPA00

	AP15	SYSACE_MPA01	69	MPA01

	AG17	SYSACE_MPA02	68	MPA02

	AH17	SYSACE_MPA03	67	MPA03

	AG15	SYSACE_MPA04	45	MPA04

	AF15	SYSACE_MPA05	44	MPA05

	AK14	SYSACE_MPA06	43	MPA06

	AJ15	SYSACE_MPBRDY	39	MPBRDY

	AJ14	SYSACE_MPCE	42	MPCE

	L9	SYSACE_MPIRQ	41	MPIRQ

	AL15	SYSACE_MPOE	77	MPOE

	AL14	SYSACE_MPWE	76	MPWE

	AC8	SYSACE_CFGTDI	81	CFGTDI

	AE8	FPGA_TCK	80	CFGTCK

	AD8	FPGA_TDI	82	CFGTDO

	AF8	FPGA_TMS	85	CFGTMS

	AE16	CLK_33MHZ_SYSACE(1)	93	CLK

Notes:

1. The System ACE CF clock is sourced from U28 32.000 MHz osc.

References

See the System ACE CF product page and the System ACE CompactFlash Solution Data Sheet. [Ref 18]

ML605 Hardware User Guide	www.xilinx.com	25
UG534 (v1.2.1) January 21, 2010

Image 25

Xilinx ML605 manual 6System ACE CF Connections U1 Fpga Pin Schematic Net Name

Contents

UG534 v1.2.1 January 21, 2010 optional ML605 Hardware User Guide Date Version Revision Revision History Table of Contents ML605 Hardware User Guide About This Guide Preface About This Guide Additional Support Resources Additional Information ML605 Evaluation Board ML605 Evaluation Board FeaturesSMA IIC Eeprom 1 KB Fpga Init Fpga Done Overview 1ML605 High-Level Block Diagram Block Diagram Feature ML605 FeaturesDetailed Description DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Virtex-6 XC6VLX240T-1FFG1156 Fpga Configuration Voltage Rails 2Virtex-6 Fpga Configuration Modes M20Cclk Direction 3Voltage Rails U1 Fpga Bank Detailed Description 3Voltage Rails Cont’d U1 Fpga Bank MB DDR3 Memory SodimmVCC1V5FPGA 4DDR3 Sodimm Connections DDR3A9 ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref MB Linear BPI Flash Mb Platform Flash XL ML605 Flash Boot Options FLASHD1 DQ1 FLASHD0 DQ0FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers 8ML605 Oscillator Pin 1 Location Identifiers SMA Connectors Differential Smarefclkn SMA PinSmarefclkp ICS Multi-Gigabit Transceivers GTX MGTs 12PCIe Lane Size Select Jumper J42 PCI Express Endpoint Connectivity 8PCIe Edge Connector Connections AA4 PCIERX7N AA3 PCIERX7PPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 12Board Connections for PHY Configuration Pins 11PHY Default Interface Mode Jumper Settings J66 J67 J6811 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 Sgmii GTX Transceiver Clock Generation 12Board Connections for PHY Configuration Pins Cont’d13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 RXD4 PHYRXD4PHYRXD5 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Status LEDs Designator Signal Name Color Label Description 16Ethernet PHY Status LEDs Ethernet PHY Status LEDs Fpga Init and Done LEDs User I/OControlled LED Fpgainitb User LEDs 18User LEDs and Gpio Connector, Directional LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED Switch Pin User DIP Switch Usersmagpion User SMA GpioUsersmagpiop J41 Pin LCD Display 16 Character x 2 Lines Power On/Off Slide Switch SW2 Switches Fpgaprogb Pushbutton SW4 Active-Low Sysaceresetb Pushbutton SW3 Active-Low 26System ACE CF CompactFlash Image Select DIP Switch S1 System ACE CF CompactFlash Image Select DIP Switch S1 M20 Bus Width 26ML605 Configuration Modes Master BPI Vita 57.1 FMC HPC Connector HPC Pin 28VITA 57.1 FMC HPC Connections 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB08P FMCHPCHB09NFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d VIOBM2C Vadj VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector LPC Pin 30VITA 57.1 FMC LPC Connections AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d 28ML605 Onboard Power Regulators Onboard Power Regulation Vccintfpga UCD9240PFCVccaux UCD7230RGWR 29System Monitor External Reference System Monitor System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Function/Type Default Table A-1Default Switch Settings Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF NET DDR3D9 Appendix C ML605 Master UCF NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References