16USB Controller Connections, U81 USB Controller | Xilinx ML605

Chapter 1: ML605 Evaluation Board

13. USB Controller

The ML605 provides USB support via a Cypress CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller (U81). The host port is a USB Type-A connector (J5). A USB keyboard (without an internal USB hub) will be able to connect to this USB Host port to demonstrate functionality. The peripheral port is a USB Type Mini- B (J20).

Table 1-16:USB Controller Connections

	U1 FPGA			U81 USB Controller
		Schematic Net Name
			Pin
	Pin			Pin Name
	Pin
			Number
			Number

	Y32	USB_A0_LS	52	GPIO19_A0_CS0_52

	W26	USB_A1_LS	50	50_GPIO20_A1_CS1

	W27	USB_CS_B_LS	49	49_GPIO21_CS_N

	R33	USB_D0_LS	94	GPIO0_D0_94

	R34	USB_D1_LS	93	GPIO1_D1_93

	T30	USB_D2_LS	92	GPIO2_D2_92

	T31	USB_D3_LS	91	GPIO3_D3_91

	T29	USB_D4_LS	90	GPIO4_D4_90

	V28	USB_D5_LS	89	GPIO5_D5_89

	V27	USB_D6_LS	87	GPIO6_D6_87

	U25	USB_D7_LS	86	GPIO7_D7_86

	Y28	USB_D8_LS	66	GPIO8_D8_MISO_66

	W32	USB_D9_LS	65	GPIO9_D9_nSSI_65

	W31	USB_D10_LS	61	GPIO10_D10_SCK_61

	Y29	USB_D11_LS	60	GPIO11_D11_MOSI_60

	W29	USB_D12_LS	59	GPIO12_D12_59

	Y34	USB_D13_LS	58	GPIO13_D13_58

	Y33	USB_D14_LS	57	GPIO14_D14_57

	Y31	USB_D15_LS	56	GPIO15_D15_SSI_N_56

	Y27	USB_INT_LS	46	46_GPIO24_INT_IORDY_IRQ0

	W25	USB_RD_B_LS	47	47_GPIO23_RD_N_IOR

	T25	USB_RESET_B_LS	85	RESET_N_85

	V25	USB_WR_B_LS	48	48_GPIO22_WR_N_IOW

References

See the Cypress CY7C67300 Data Sheet for more information. [Ref 29]

In addition, see the USB Specifications for more information. [Ref 30]

The FPGA requires implementation of a peripheral controller in order to communicate with the Cypress USB device. See the XPS External Peripheral Controller (EPC) v1.02a Data Sheet for more information. [Ref 20]

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		UG534 (v1.2.1) January 21, 2010

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Xilinx ML605 manual 16USB Controller Connections, U81 USB Controller

Contents

ML605 Hardware User Guide UG534 v1.2.1 January 21, 2010 optional Revision History Date Version Revision Table of Contents ML605 Hardware User Guide About This Guide Additional Support Resources Preface About This Guide ML605 Evaluation Board Additional Information Features ML605 Evaluation BoardSMA IIC Eeprom 1 KB Overview Fpga Init Fpga Done Block Diagram 1ML605 High-Level Block Diagram ML605 Features FeatureDetailed Description DDR3 Sodimm Sgmii ML605 Evaluation Board ML605 Features Cont’dWDW6TP Configuration Virtex-6 XC6VLX240T-1FFG1156 Fpga 2Virtex-6 Fpga Configuration Modes M20 Voltage RailsCclk Direction 3Voltage Rails U1 Fpga Bank MB DDR3 Memory Sodimm Detailed Description 3Voltage Rails Cont’d U1 Fpga BankVCC1V5FPGA 4DDR3 Sodimm Connections ML605 Evaluation Board 4DDR3 Sodimm Connections Cont’d DDR3A9 DDR3D30 DQ30 DDR3DM0 See the Micron Technology, Inc. for more information Ref Mb Platform Flash XL MB Linear BPI Flash ML605 Flash Boot Options FLASHD0 DQ0 FLASHD1 DQ1FLASHD2 DQ2 FLASHD3 DQ3 Fpga Design Considerations for the Configuration Flash System ACE CF and CompactFlash Connector 6System ACE CF Connections U1 Fpga Pin Schematic Net Name USB Jtag Oscillator Differential Clock GenerationOscillator Socket Single-Ended 7ML605 Oscillator Socket Pin 1 Location Identifiers SMA Connectors Differential 8ML605 Oscillator Pin 1 Location Identifiers Smarefclkn SMA PinSmarefclkp Multi-Gigabit Transceivers GTX MGTs ICS PCI Express Endpoint Connectivity 12PCIe Lane Size Select Jumper J42 8PCIe Edge Connector Connections AA3 PCIERX7P AA4 PCIERX7NPCIE100MMGT0P GTXE1X0Y6 SFP Module Connector 11PHY Default Interface Mode Jumper Settings J66 J67 J68 12Board Connections for PHY Configuration Pins11 /100/1000 Tri-Speed Ethernet PHY Bit2 Bit1 Bit0 12Board Connections for PHY Configuration Pins Cont’d Sgmii GTX Transceiver Clock Generation13Ethernet PHYConnections U1 Fpga Pin U80 M88E1111 PHYRXD4 RXD4PHYRXD5 RXD5 Vbus USB-to-UART BridgeGround 16USB Controller Connections USB ControllerU81 USB Controller 17DVI Controller Connections DVI CodecU38 Chrontel CH7301C IIC Bus 14IIC Bus Topology Iicsdamain SDA Kb NV MemoryIicsclmain SCL Designator Signal Name Color Label Description Status LEDs Ethernet PHY Status LEDs 16Ethernet PHY Status LEDs User I/O Fpga Init and Done LEDsControlled LED Fpgainitb 18User LEDs and Gpio Connector, Directional LEDs User LEDs Detailed Description 21User LED Connections Fpga U1 Pin User Pushbutton SwitchesGpio J62 Pin Controlled LED User DIP Switch Switch Pin Usersmagpion User SMA GpioUsersmagpiop LCD Display 16 Character x 2 Lines J41 Pin Switches Power On/Off Slide Switch SW2 Sysaceresetb Pushbutton SW3 Active-Low Fpgaprogb Pushbutton SW4 Active-Low System ACE CF CompactFlash Image Select DIP Switch S1 26System ACE CF CompactFlash Image Select DIP Switch S1 26ML605 Configuration Modes M20 Bus Width Vita 57.1 FMC HPC Connector Master BPI 28VITA 57.1 FMC HPC Connections HPC Pin 28VITA 57.1 FMC HPC Connections Cont’d FMCHPCHB09N FMCHPCHB08PFMCHPCHB13P FMCHPCHB08N Detailed Description 28VITA 57.1 FMC HPC Connections Cont’d Vadj VIOBM2C VadjVREFAM2C Vadj VREFBM2C Vita 57.1 FMC LPC Connector 30VITA 57.1 FMC LPC Connections LPC Pin AC Adapter and Input Power Jack/Switch Power ManagementDetailed Description 30VITA 57.1 FMC LPC Connections Cont’d Onboard Power Regulation 28ML605 Onboard Power Regulators UCD9240PFC VccintfpgaVccaux UCD7230RGWR System Monitor 29System Monitor External Reference System Monitor Header J35 12V Supply Monitor Fan Controller Bank Configuration Options Configuration Options ML605 Evaluation Board Table A-1Default Switch Settings Function/Type Default Gmii Vita 57.1 FMC LPC J63 and HPC J64 Connector Pinout Figure B-2FMC HPC Connector Pinout ML605 Master UCF Appendix C ML605 Master UCF NET DDR3D9 NET DDR3DQS0P NET FLASHA21 ML605 Hardware User Guide UG534 v1.2.1 January 21 NET FMCHPCHB03P NET FMCHPCLA16N NET FMCLPCPRSNTM2CL NET Iicsdadvi NET PCIERX2N NET Pmbusdatals NET Sfplos NET Sfprxn NET Sfprxp NET USBD6LS References Appendix D References