Xilinx PLB PCI Full Bridge specifications User Asserted PCI Interrupt Signal

						PLB PCI Full Bridge (v1.00a)
Table 2: PLB PCI Bridge I/O Signals (Contd)
	Port	Signal Name		Interface	I/O	Description
	P72	IRDY_I		Internal	O	Input from PCI Bus IRDY_N availalble at top-level as
						output from bridge
		PCI 64-bit Extensions (reserved for future support of 64-bit PCI)
	P73	PAR64		PCI Bus	I/O	Generates and checks even parity across AD[63:32]
						and CBE[7:4]
						Indicates that a target has decoded the address
	P74	ACK64_N		PCI Bus	I/O	presented during the address phase and is claiming
						the transaction as a 64-bit target
	P75	REQ64_N		PCI Bus	I/O	Driven by the initiator to indicate a 64-bit bus
						transaction
				User Asserted PCI Interrupt Signal
						Active high signal to asynchronously assert INTR_A.
	P76	Bus2PCI_INTR		Internal	I	Inverted signal drives INTR N user application input
						of v3.0 core. See v3.0 core documents for details on
						INTR N functionality.
				Virtex-4 Only, IDELAY Clock
	P77	RCLK		Internal	I	200 MHz clock input to IDELAY elements of Virtex-4
						buffers. Ignored if not Virtex-4 architecture.
			PCI Bus Monitoring Debug Vector Signal
	P78	PCI_monitor(0:47)		Internal	O	Output vector to monitor PCI Bus.

Notes:

1.This signal’s function and timing are defined in the IBM 64-Bit Processor Local Bus Architecture Specification Version 3.5.

The REQ_N_toArb facilitates an interface to an internal (i.e., in the FPGA) pci arbiter. The v3.0 input buffer for GNT_N is removed. This allows an internal connection to GNT N when using an internal arbiter. When an external arbiter is used, GNT_N_fromArb is not needed.

REQ_N is a 3-stated I/O. The REQ N toArb port is available to maintain a v3.0 core-like interface. The REQ_N_toArb port allows the use of the same port list for PCI bus interface and the ucf-file for the v3.0 core is the standard file.

The v3.0 core requires that GNT N be asserted for two clock cycles to initiate a transaction upon receiving grants.

Bus2PCI_INTR is an active High signal. It allows asynchronous assertion of INTR_A on the PCI bus. The signal is driven by user supplied circuitry (i.e., a PLB GPIO IP core). If it is not connected in the mhs-file, then EDK 8.1 tools will tie the signal Low. The signal is inverted in the PLB PCI Bridge and AND’d with the bridge interrupt signal (active Low) to drive the INTR_N input of the v3.0 core. This signal then asynchronously drives INTR_A on the PCI bus. See the v3.0 core specifications on INTR_A behavior relative to v3.0 input INTR_N. The v3.0 core command register interrupt disable bit controls the INTR_A operation and v3.0 core status register Interrupt status bit flags if v3.0 core INTR_A is asserted.

DS508 March 21, 2006 www.xilinx.com 17

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