Xilinx PLB PCI Full Bridge specifications Bus Interface Parameters, Address Translation

PLB PCI Full Bridge (v1.00a)

core. These documents detail the v3.0 core operation, including configuration cycles, and are available from Xilinx.

As required by the LogiCORE v3.0 core, GNT_N must be asserted for two clock cycles to initiate a PCI transaction by the PLB PCI Bridge.

Bus Interface Parameters

Because many features in the IPIF v3.0 Bridge design can be parameterized, the user can realize a PLB PCI Full Bridge uniquely tailored while using only the resources required for the desired functionality. This approach also achieves the best possible performance with the lowest resource usage. Table 1 shown the features that can be parameterized in the PLB PCI Bridge design.

Address Translation

Address space on the PCI side that is accessible from the PLB side must be translated to a 2N contiguous block on the PLB side. Up to six contiguous blocks are possible. Each block has parameters for base address (C_IPIFBAR_N), high address, address translation vector, and memory designator (memory or I/O).

All address space on the PLB side that is accessible from the PCI side must be translated to a maximum of three 2N contiguous blocks on the PCI side. Up to three blocks are possible because the LogiCore PCI v3.0 core supports up to 3 BARs. Each block has parameters for length, which must be a 2N range, and address translation vector. Only PCI memory space is supported.

Address translations in both directions are performed as follows:

•High-order address bits are substituted for the address vector before crossing to the other bus domain. The number of high-order bits substituted in the PLB address presented to the bridge is given by the number of bits that are the same between the C IPIFBAR N and C IPIF_HIGHADDR_N parameters. The number of high-order bits substituted in the PCI address presented to the bridge for a translation from PCI to PLB domains is given by the bus width minus the parameter C_PCIBAR_LEN_N.

•The low-order bits are transferred directly between bus domains. The bits substituted in a translation from PLB to PCI domains can be selected via a parameter (C_INCLUDE_BAROFFSET REG) as either a parameter (C_IPIFBAR2PCIBAR_N) or a programmable register for each BAR. The bits that are substituted for in a translation from PCI to PLB domains is defined by a parameter (C_PCIBAR2IPIFBAR_M) for each BAR.

Figure 2 shows two sets of base address register (BAR) parameters and how they are used. The two sets are independent sets: one set for the up to six PLB-side device (IPIFBAR) address ranges and another set for the up to three PCI-side device (PCIBAR) address ranges.

This document includes three examples of how to use the two sets of base address register (BAR) parameters:

Example 1, shown in Figure 2, outlines the use of the two sets of BAR parameters.

Example 2 outlines the use of the IPIFBAR parameters sets for the specific address translations of PLB addresses within the range of a given IPIFBAR to a remote PCI address space.

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