Supported PCI Bus Commands, Code Name | Xilinx PLB PCI Full Bridge

PLB PCI Full Bridge (v1.00a)

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

	Generic	Parameter	Affects	Depends	Description

					If G61=0, G62 has no meaning. If
					G61=1, G62 sets the number of devices
					supported in configuration operations.
	G62	C_NUM_IDSEL	G49 and	G61 and	Must be sufficiently large to include the
	G62	C_NUM_IDSEL	G63	G63	address bit defined by G63. If G49=1,
			G63	G63	address bit defined by G63. If G49=1,
					G62 restricts the allowed values that are
					meaningful in the Device Number
					Register

					If G61=0 or G49=1, G63 has no
	G63	C_BRIDGE_IDSEL_ADDR	G62	G49, G61	meaning. If G61=1 and G49=0, G63
	G63	_BIT	G62	and G62	must be consistent with the setting of
		_BIT		and G62	must be consistent with the setting of
					G62

			IPIF Parameters Group

	G64	C_PLB_MID_WIDTH

	G65	C_PLB_NUM_MASTERS

	G66	C_PLB_AWIDTH

	G67	C_PLB_DWIDTH

	G68	C_FAMILY	G50-52		If G68 ≠ Virtex-4, G50-52 have no
	G68	C_FAMILY	G50-52		meanings.
					meanings.

Supported PCI Bus Commands

The list of commands supported by the LogiCORE PCI interface is provided in Table 4.

Table 4: Supported PCI Bus Commands

	Command		PLB PCI Bridge

Code	Name	Target		Initiator

0000	Interrupt Acknowledge	No		No

0001	Special Cycle	No		No

0010	I/O Read	No		Yes

0011	I/O Write	No		Yes

0100	Reserved	Ignore		Ignore

0101	Reserved	Ignore		Ignore

0110	Memory Read	Yes		Yes

0111	Memory Write	Yes		Yes

1000	Reserved	Ignore		Ignore

1001	Reserved	Ignore		Ignore

1010	Configuration Read	Yes		Optional

1011	Configuration Write	Yes		Optional

1100	Memory Read Multiple	Yes		Yes

22	www.xilinx.com	DS508 March 21, 2006
		Product Specification

Image 22

Xilinx PLB PCI Full Bridge specifications Supported PCI Bus Commands, Command PLB PCI Bridge, Code Name, Initiator

Contents

Introduction LogiCORE Facts Features PLB PCI Full Bridge v1.00a PLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core Requirements Bus Interface Parameters Address Translation Example Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 Cplbawidth IPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0 Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOA Configuration V3.0 Core Parameters Group Ipif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System Signals Port Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0 PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1 V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code Name PLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr + Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers Descriptions PLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicates PLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description Cincludebaroffsetreg CIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit bus Transaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchable Translation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target Perr PLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory Write Configuration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design Tools Design Debug Design Contraints NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 Support PLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision