Xilinx PLB PCI Full Bridge

PLB PCI Full Bridge (v1.00a)

DS508 March 21, 2006 www.xilinx.com 21

Product Specification

EARLY ACCESS

G43 C_NUM_PCI_RETRIES_IN

_WRITES

G44

C_NUM_PCI_PRDS_BET

WN_RETRIES_IN_

WRITES

G45 C_NUM_IPIF_RETRIES_

IN_WRITES

G46 C_BASEADDR G47 G47

G46 to G47 define range in PLB-memory

space that is responded to by PLB PCI

bridge register address space

G47 C_HIGHADDR G46 G46

G46 to G47 define range in PLB-memory

space that is responded to by PLB PCI

bridge register address space

G48 C_INCLUDE_BAROFFSET

_REG

G4, G8,

G12, G16,

G20 and

G24

If G48=1, G4, G8, G12, G16, G20 and

G24 have no meaning. The number of

registers included is set by G1

G49 C_INCLUDE_DEVNUM_

REG G63 G61, G62

If G61=0, G49 has no meaning. If G49

and G61=1, G63 has no meaning.

Meaningful bits in the Device Number

G50 C_NUM_IDELAYCTRL G68 If G68 ≠ Virtex-4, G50 has no meaning

G51 C_INCLUDE_GNT_DELAY G68 If G68 ≠ Virtex-4, G51 has no meaning

G52 C_IDELAYCTRL_LOC G50 and

G68

If G68 ≠ Virtex-4, G52 has no meaning. If

G68=Virtex-4, G52 must include the

number of LOC coordinates specified by

G50

v3.0 Core Parameters Group

G53 C_DEVICE_ID

G54 C_VENDOR_ID

G55 C_CLASS_CODE

G56 C_REV_ID

G57 C_SUBSYSTEM_ID

G58 C_SUBSYSTEM_VENDOR

_ID

G59 C_MAX_LAT

G60 C_MIN_GNT

Configuration

G61 C_INCLUDE_PCI_

CONFIG

G62, G63,

P62

If G61=1, signal P62 has an internal

connection and the top-level port P62

has no internal connection

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

Generic Parameter Affects Depends Description