V3.0 Core Parameters Group | Xilinx PLB PCI Full Bridge instruction

									PLB PCI Full Bridge (v1.00a)

			Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

				Generic	Parameter		Affects	Depends	Description

				G43	C_NUM_PCI_RETRIES_IN
				G43	_WRITES
					_WRITES

					C_NUM_PCI_PRDS_BET
				G44	WN_RETRIES_IN_
					WRITES

				G45	C_NUM_IPIF_RETRIES_
				G45	IN_WRITES
					IN_WRITES

									G46 to G47 define range in PLB-memory
				G46	C_BASEADDR		G47	G47	space that is responded to by PLB PCI
									bridge register address space

									G46 to G47 define range in PLB-memory
				G47	C_HIGHADDR		G46	G46	space that is responded to by PLB PCI
									bridge register address space

							G4, G8,		If G48=1, G4, G8, G12, G16, G20 and
					C_INCLUDE_BAROFFSET		G12, G16,		If G48=1, G4, G8, G12, G16, G20 and
				G48	C_INCLUDE_BAROFFSET		G12, G16,	G1	G24 have no meaning. The number of
				G48	_REG		G20 and	G1	G24 have no meaning. The number of
					_REG		G20 and		registers included is set by G1
							G24		registers included is set by G1
							G24

									If G61=0, G49 has no meaning. If G49
				G49	C_INCLUDE_DEVNUM_		G63	G61, G62	and G61=1, G63 has no meaning.
				G49	REG		G63	G61, G62	Meaningful bits in the Device Number
					REG				Meaningful bits in the Device Number
									register are defined by G62

				G50	C_NUM_IDELAYCTRL			G68	If G68 ≠ Virtex-4, G50 has no meaning

				G51	C_INCLUDE_GNT_DELAY			G68	If G68 ≠ Virtex-4, G51 has no meaning

									If G68 ≠ Virtex-4, G52 has no meaning. If
				G52	C_IDELAYCTRL_LOC			G50 and	G68=Virtex-4, G52 must include the
				G52	C_IDELAYCTRL_LOC			G68	number of LOC coordinates specified by
								G68	number of LOC coordinates specified by
									G50

						v3.0 Core Parameters Group

				G53	C_DEVICE_ID

				G54	C_VENDOR ID

				G55	C_CLASS CODE

				G56	C_REV ID

				G57	C_SUBSYSTEM ID

				G58	C SUBSYSTEM VENDOR
				G58	ID
					ID

				G59	C MAX LAT

				G60	C MIN_GNT

							Configuration

					C_INCLUDE_PCI_		G62, G63,		If G61=1, signal P62 has an internal
				G61	C_INCLUDE_PCI_		G62, G63,		connection and the top-level port P62
				G61	CONFIG		P62		connection and the top-level port P62
					CONFIG		P62		has no internal connection
									has no internal connection


	DS508 March 21, 2006						www.xilinx.com		21
	Product Specification

Image 21

Xilinx PLB PCI Full Bridge specifications V3.0 Core Parameters Group

Contents

LogiCORE Facts Introduction PLB PCI Full Bridge v1.00a Features PLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core Requirements Address Translation Bus Interface Parameters Example Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 Cplbawidth BAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0 Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOA V3.0 Core Parameters Group Configuration Ipif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System Signals Port Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0 PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1 V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code Name PLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr + PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter Dependencies Bits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicates PLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register Description CIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register Description Remote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchable Translation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI Target PLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration Transactions Configuration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design Implementation Design Contraints Design Debug NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target Technology PLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision