Xilinx PLB PCI Full Bridge NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33

Models: PLB PCI Full Bridge

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PLB PCI Full Bridge (v1.00a)

The constraints are also implemented automatically in the EDK tool flow with any tool option that invokes bridge synthesis. In this flow, tcl-scripts generate the ucf-file constraints and place them in a file in the OPB PCI Bridge directory of the project implementation directory. The ucf-file constraints are then included in the ngc-file generated in the EDK tool flow. The user can check the ucf-file in the implementation directory of the bridge directory to verify that the constraints are included. As noted above, the user can include all constraints in the top-level ucf-file. When the constraints are included in both the top-level ucf-file and the bridge ngc-file (via the bridge directory ucf-file), then the top-level ucf-file overrides any conflicting constraints in the bridge ngc-file.

To remind the user that the following constraints must be included, PLATGEN will generate the message:

The OPB PCI Bridge design requires design constraints to guarantee performance. Please refer to the OPB IPIF/LogiCORE PCI64 v3.0 bridge design data sheet for details.

Additional bridge specific constraints are required and an example ucf-file is provided in the EDK pcores library. To remind the user that the additional bridge related constraints must be included in the top-level ucf-file, PLATGEN will generate the message:

An example UCF is available for this core and must be modified for use in the system. Please refer to the EDK Getting Started guide for the location of this file.

The constraints that the LogiCORE PCI64 v3.0 core require to meet PCI specifications are shown below.

All io buffers must have IOB=TRUE

IOSTANDARD must explicitly list PCI33_3. Both BYPASS IOBDELAY=BOTH must be included for all PIC ports, as shown below.

NET "PCI AD(*)" IOSTANDARD=PCI33 3;

NET "PCI CBE(*)" IOSTANDARD=PCI33 3;

NET "PCI PAR" IOSTANDARD=PCI33 3; NET "PCI FRAME N" IOSTANDARD=PCI33 3; NET "PCI TRDY N" IOSTANDARD=PCI33 3; NET "PCI IRDY N" IOSTANDARD=PCI33 3; NET "PCI STOP N" IOSTANDARD=PCI33 3; NET "PCI DEVSEL N" IOSTANDARD=PCI33 3; NET "PCI PERR N" IOSTANDARD=PCI33 3; NET "PCI SERR N" IOSTANDARD=PCI33 3; #Include next 2 if routed to pins NET "IDSEL" IOSTANDARD=PCI33 3;

NET "GNT N" IOSTANDARD=PCI33 3;

NET "PCI AD(*)" BYPASS;

NET "PCI CBE(*)" BYPASS;

NET "PCI_PAR" BYPASS;

NET "PCI_FRAME_N" BYPASS;

NET "PCI_TRDY_N" BYPASS;

NET "PCI_IRDY_N" BYPASS;

NET "PCI_STOP_N" BYPASS;

NET "PCI_DEVSEL_N" BYPASS;

NET "PCI_PERR_N" BYPASS;

NET "PCI_SERR_N" BYPASS;

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DS508 March 21, 2006

 

 

Product Specification

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Xilinx PLB PCI Full Bridge specifications NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33