Xilinx PLB PCI Full Bridge Bar, IPIFBAR0 Cplbawidth, LEN0, CPCIBAR2IPI, FBAR1 PLB Awidth

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic	Feature /	Parameter	Allowable Values	Default	VHDL
	Description	Name		Value	Type
	IPIF BAR to which PCI	C_PCIBAR2	Vector of length		std_logic_
G27	BAR 0			0x00000000
	is mapped	IPIFBAR_0	C_PLB_AWIDTH		vector
	Power of 2 in the size in	C_PCIBAR_
G28	bytes of PCI BAR 0		5 to 29	16	integer
		LEN_0
	space
G29	IPIF BAR to which PCI	C_PCIBAR2IPI	Vector of length	0x00000000	std_logic_
	BAR 1 is mapped	FBAR_1	C PLB AWIDTH		vector
	Power of 2 in the size in	C_PCIBAR_
G30	bytes of PCI BAR 1		5 to 29	16	integer
		LEN_1
	space
G31	IPIF BAR to which PCI	C_PCIBAR2	Vector of length	0x00000000	std_logic_
	BAR 2 is mapped	IPIFBAR_2	C PLB AWIDTH		vector
	Power of 2 in the size in	C_PCIBAR_
G32	bytes of PCI BAR 2		5 to 29	16	integer
		LEN_2
	space
G33	PCI address bus width	C_PCI_ABUS_	32	32	integer
		WIDTH
G34	PCI data bus width	C_PCI_DBUS_	32	32	integer
		WIDTH
	Both PCI2IPIF FIFO
	address bus widths.	C PCI2IPIF_
G35	Usable depth is	FIFO ABUS_	4-14	9	integer
	2^C PCI2IPIF FIFO A	WIDTH
	BUS WIDTH - 3
	Both IPIF2PCI FIFO
	address bus widths.	C IPIF2PCI_
G36	Usable depth is	FIFO ABUS_	4-14	9	integer
	2^C IPIF2PCI FIFO A	WIDTH
	BUS WIDTH - 3
	Include explicit
G37	instantiation of INTR A	C INCLUDE_	0 = not included	1	integer
	io-buffer (must be 1 to	INTR A BUF	1 = included
	include io-buffer)
	Include explicit
G38	instantiation of REQ N	C INCLUDE_	0 = not included	1	integer
	io-buffer (must be 1 to	REQ N BUF	1 = included
	include io-buffer)
	Minimum PCI2IPIF		5 to the lesser of 24 or
	FIFO occupancy level	C_TRIG_PCI_	the PCI2IPIF FIFO
	that triggers the bridge		DEPTH-3. PCI2IPIF
G39		READ_OCC_		32	integer
	to initiate a prefetch PCI		FIFO DEPTH given by
		LEVEL
	read of a remote PCI		2^C_PCI2IPIF_FIFO_
	agent		ABUS_WIDTH

10	www.xilinx.com	DS508 March 21, 2006
		Product Specification