Xilinx PLB PCI Full Bridge specifications Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6

PLB PCI Full Bridge (v1.00a)

The parameter C_IDELAYCTRL_LOC has the syntax of IDELAYCTRL_XNYM where N and M are coordinates and multiple entries are concatenated by "-" (i.e., dash). The order of entries correspond to IDELAYCNTRL instance names XPCI_IDC0, XPCI_IDC1, ... up to the maximum index of IDELAY controller instances in the user’s board design. The maximum index is C_NUM_IDELAYCTRL-1. To use the parameter to set the LOC constraint in the core level ucf-file for the above example, the parameter should be set in the MHS-file as shown below.

PARAMETER C_IDELAYCTRL_LOC="IDELAYCTRL_X2Y5-IDELAYCTRL_X2Y6"

The quotes are optional. The actual number of IDELAYCTRL primitives and corresponding LOC constraints depends on the user’s PCI pinout and part used.

Other constraints that are required include the IOBDELAY TYPE, IOBDELAY VALUE and IOB. These parameters are set in the normal EDK tool flow, but can be included in the system top-level ucf-file. For alternative tool flows, the setting are shown below. The settings shown below are settings at the time this document was written. The LogiCORE v3 PCI core Implementation Guide and v3.0 core ucf generator tool should be checked for updated values. IOSTANDARD must be explicitly defined in the ucf-file with the BYPASS constraint for ISE 8.1 tools; this can change in with future versions of the tools.

#-------------------------------------------------------------------------
# Virtex-4	Only Constraints
#-------------------------------------------------------------------------
INST "*XPCI_CBD*"		IOBDELAY TYPE=VARIABLE ;
INST "*XPCI_ADD*"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_PARD"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_FRAMED"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_TRDYD"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_IRDYD"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI_CORE/XPCI_STOPD"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI CORE/XPCI DEVSELD"		IOBDELAY TYPE=VARIABLE ;
INST "*PCI CORE/XPCI PERRD"		IOBDELAY_TYPE=VARIABLE ;
INST "*PCI CORE/XPCI SERRD"		IOBDELAY_TYPE=VARIABLE ;
#Include next 2 if routed to pins
INST "*XPCI IDSEL"		IOBDELAY_TYPE=VARIABLE ;
INST "*XPCI GNTD"		IOBDELAY_TYPE=VARIABLE ;
INST "*XPCI CBD*"		IOBDELAY_VALUE=55 ;
INST "*XPCI ADD*"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI PARD"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI FRAMED"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI TRDYD"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI IRDYD"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI STOPD"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI DEVSELD"		IOBDELAY_VALUE=55 ;
INST "*PCI CORE/XPCI PERRD"		IOBDELAY_VALUE=55 ;
INST "*PCI_CORE/XPCI_SERRD"		IOBDELAY_VALUE=55 ;
#Include next 2 if routed to pins
INST "*XPCI_IDSEL"		IOBDELAY_VALUE=55 ;
INST "*XPCI_GNTD"		IOBDELAY_VALUE=55 ;

Some of the Virtex-4 constraints are implemented automatically in the EDK tool flow with any tool option that invokes bridge synthesis. As described earlier, tcl-scripts generate the ucf-file constraints and place them in a file in the OPB PCI Bridge directory of the project implementation directory. The ucf-file constraints are then included in the ngc-file generated in the EDK tool flow. The user can check

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