Xilinx PLB PCI Full Bridge Generic Feature Parameter Allowable Values Default, Description Name

PLB PCI Full Bridge (v1.00a)

Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus.

Table 1: PLB PCI Bridge Interface Design Parameters

Generic	Feature /	Parameter	Allowable Values	Default	VHDL
	Description	Name		Value	Type
		Bridge Features Parameter Group
			1-6; Parameters listed
			below corresponding to
			unused BARs are
		C_IPIFBAR	ignored, but must be
G1	Number of IPIF devices		valid values. BAR label	6	integer
		_NUM
			0 is the required bar for
			all values 1-6 and the
			index increments from 0
			as BARs are added
G2	IPIF device 0 BAR	C_IPIFBAR_0	Valid PLB address (1)	0xFFFFFFFF	std_logic_
					vector
G3	IPIF BAR high address	C_IPIFBAR_	Valid PLB address (1)	0x00000000	std_logic_
	0	HIGHADDR_0			vector
	PCI BAR to which IPIF
	BAR 0 is mapped	C_IPIFBAR2	Vector of length		std_logic_
G4	unless			0xFFFFFFFF
	C_INCLUDE_BAROFF	PCIBAR_0 1	C PLB AWIDTH		vector
	SET_REG = 1
G5	IPIF BAR 0 memory	C_IPIF_SPACE	0 = I/O space	1	integer
	designator	TYPE 0	1 = Memory space
G6	IPIF device 1 BAR	C IPIFBAR_1	Valid PLB address (1)	0xFFFFFFFF	std_logic_
					vector
G7	IPIF BAR high address	C IPIFBAR_	Valid PLB address (1)	0x00000000	std_logic_
	1	HIGHADDR_1			vector
	PCI BAR to which IPIF
	BAR 1 is mapped	C IPIFBAR2	Vector of length		std_logic_
G8	unless			0xFFFFFFFF
	C INCLUDE BAROFF	PCIBAR 1	C_PLB_AWIDTH		vector
	SET REG = 1
G9	IPIF BAR 1 memory	C IPIF SPACE	0 = I/O space	1	integer
	designator	TYPE 1	1 = Memory space
G10	IPIF device 2 BAR	C IPIFBAR_2	Valid PLB address (1)	0xFFFFFFFF	std_logic_
					vector
G11	IPIF BAR high address	C IPIFBAR_	Valid PLB address (1)	0x00000000	std_logic_
	2	HIGHADDR_2			vector
	PCI BAR to which IPIF
	BAR 2 is mapped
G12	unless	C_IPIFBAR2	Vector of length	0xFFFFFFFF	std_logic_
	C_INCLUDE_BAROFF	PCIBAR_2	C_PLB_AWIDTH		vector
	SET_
	REG = 1

8	www.xilinx.com	DS508 March 21, 2006
		Product Specification