PLB PCI Full Bridge (v1.00a)
Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic | Feature / | Parameter | Allowable Values | Default | VHDL | |
Description | Name | Value | Type | |||
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| Include configuration | C_INCLUDE_ | 0 = Not included |
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G61 | functionality via IPIF | 1 | integer | |||
PCI_CONFIG | 1 = Included | |||||
| transactions |
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G62 | Number of IDSEL | C_NUM_ | 1 to 16 | 8 | integer | |
signals supported | IDSEL | |||||
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| 31 down to 16 |
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| PCI address bit that PCI | C_BRIDGE_ | Must be <= 15 + |
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G63 | v3.0 core IDSEL is | IDSEL_ADDR_ | C_NUM_IDSEL. | 16 | integer | |
| connected to | BIT | AD(31 down to 0) index |
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| IPIF Parameters Group |
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| PLB master ID bus | C_PLB_MID_ | log2(C PLB NUM MA |
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G64 | width (set automatically | 3 | integer | |||
| by XPS) | WIDTH | STERS) |
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| Number of masters on | C_PLB_NUM |
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G65 | PLB bus (set | 8 | integer | |||
MASTERS | ||||||
| automatically by XPS) |
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G66 | PLB Address width | C_PLB_ | 32 (only allowed value | 32 | integer | |
AWIDTH | ||||||
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G67 | PLB Data width | C_PLB_ | 64 (only allowed value | 64 | integer | |
DWIDTH | ||||||
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G68 | Specifies the target | C_FAMILY | See PLB IPIF data | virtex2 | string | |
technology | sheet | |||||
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Notes:
1. The range specified must comprise a complete, contiguous power of two range, such that the range = 2n and the n least significant bits of the Base Address are zero.
2. The minimum address range specified by C BASEADDR and C HIGHADDR must be at least 0x1FF. C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR + 1.
DS508 March 21, 2006 | www.xilinx.com | 13 |
Product Specification
