Xilinx PLB PCI Full Bridge specifications Example

PLB PCI Full Bridge (v1.00a)

Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a remote PLB address space.

PLB Bus

Note 1

PCI Bus

		BAR_10		BAR_11
PLB PCI Full Bridge
IPIF
C_IPIFBAR_NUM = 3
IPIFBAR_0 IPIFBAR_1		IPIFBAR 2	IPIFBAR 3		IPIFBAR 4	IPIFBAR 5
(high-order	(high-order	(high-order		IPIF to v3.0 LogiCORE Bridge
bit sub)	bit sub)	bit sub)
Addr to PCI	Addr to PCI	Addr to PCI
			Addr to PLB		Addr to PLB
			(high-order		(high-order	Note 2
			bit sub)		bit sub)
v3.0 LogiCORE			PCIBAR 0		PCIBAR 1	PCIBAR 2
C_PCIBAR_NUM = 2

PBAR 20

PBAR 21 PBAR_22

ds508_02_112205

Figure 2: Translation of Addresses Bus-to-Bus with High-Order Bit Substitution

Example 1

Because address translations are performed only when the PLB PCI Bridge is configured with FIFOs, the example shown in Figure 2 is for an PLB PCI Bridge configuration with FIFOs only. In this example, it is assumed that C INCLUDE BAROFFSET REG=0, therefore, the parameters C_IPIFBAR2PCIBAR_N define the high-order bits for substitution in translating the address on the PLB bus to the PCI bus.

The PLB parameters are C IPIFBAR N, C IPIF_HIGHADDR_N, and C_IPIFBAR2PCIBAR_N for N=0 to 5.

The PCI parameters are C_PCIBAR_LEN_M and C_PCIBAR2IPIFBAR_M for M=0 to 2.

Example 2

Example 2 shows of the settings of the two independent sets of base address register (BAR) parameters for specifics of address translation of PLB addresses within the range of a given IPIFBAR to a remote PCI address space. Note that this setting does not depend on the PCIBARs of the PLB PCI Bridge.

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