Xilinx specifications Features, PLB PCI Full Bridge v1.00a

PLB PCI Full Bridge (v1.00a)

Features

•Independent PLB and PCI clocks

•33 MHz, 32-bit PCI bus support

•Utilizes two pairs of FIFOs to exploit the separate master and slave PLB IPIF modules.

•Includes a master IP module for remote PCI initiator transactions, which follows the protocol for interfacing with the master IPIF module utilizing Xilinx LocalLink protocol. The PLB PCI Bridge translates the PCI initiator request to PLB IPIF master transactions.

•Includes a slave IP module for remote PLB master transactions, which follows the protocol for interfacing with the slave IPIF module utilizing Xilinx IPIC protocol. The PLB PCI Bridge translates the PLB master request to PCI initiator transactions. The SRAM-like interface is utilized at the IPIC interface for data transfers.

•The PLB IPIF slave attachment has a timer that limits the time for both read and write dataphase operations to complete. When the timer expires, Sl MErr signal is asserted. See PLB IPIF Product Specification for details.

•Full bridge functionality

-PLB Master read and write of a remote PCI target (both single and burst)

-PCI Initiator read and write to a remote PLB slave (both single and multiple).

-I/O read and I/O write commands are supported only for PLB master read and writes of PCI I/O space as designated by its associated memory designator parameter. All memory space on the PLB-side is designated as memory space in the PCI sense, therefore, I/O commands cannot be used to access memory on the PLB-side.

-Configuration read and writes are supported (including self-configuration transactions) only when upper word address lines are utilized for IDSEL lines. The Configuration Read and Write commands are automatically executed by writing to the Configuration Data Port Register. Data in the Configuration Address Port Register and the Configuration Bus Number/Subordinate Bus Number Register are used in execution of the configuration transaction per PCI 2.2 specification.

•PCI Memory Read Line (MRL) command is supported in which the v3.0 core is a target. MRL is aliased to a Memory Read command which has a single data phase on the PCI.

•PCI Memory Write Invalidate (MWI) command is supported in which the v3.0 core is a target. The v3.0 core does not support this command when it is an initiator. MWI is aliased to a Memory Write command which has a single data phase on the PCI.

•Supports up to 6 PLB devices, in the sense defined by independent parameters and unique PLB memory space for each device

-Each device has the following parameters: PLB BAR, high (upper) address, memory designator, and translation for mapping PLB address space to PCI address space. Byte addressing integrity is maintained by default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition can be done with parameters or dynamically via registers.

•Supports up to 3 PCI devices (or BARs in PCI context) with unique memory PCI memory space. The v3.0 core supports up to 3 PCI BAR.

-Each device has the following parameters: PCI BAR, length, memory designator, and translation for mapping PCI address space to PLB address space. Byte addressing integrity is maintained by

2	www.xilinx.com	DS508 March 21, 2006
		Product Specification