CIPIFSPACETYPE0=1 | Xilinx PLB PCI Full Bridge manual

PLB PCI Full Bridge (v1.00a)

The example below shows how the IPIFBAR2PCIBAR_N registers assignments define translation of PLB addresses within the range of a given IPIFBAR to PCI address space.

Setting C_INCLUDE_BAROFFSET_REG=1 includes high-order bit registers for all IPIFBARs defined by C_IPIFBAR_NUM.

In this example where C_IPIFBAR_NUM=4, the following assignments for each range are made.

C_IPIFBAR_0=0x12340000

C_IPIF_HIGHADDR_0=0x1234FFFF

C_IPIFBAR2PCIBAR_0=Don’t care

C_IPIF_SPACETYPE_0=1

C_IPIFBAR_1=0xABCDE000

C_IPIF_HIGHADDR_1=0xABCDFFFF

C_IPIFBAR2PCIBAR_1=Don’t care

C_IPIF_SPACETYPE_1=0

C_IPIFBAR_2=0xFE000000

C_IPIF_HIGHADDR_2=0xFFFFFFFF

C_IPIFBAR2PCIBAR_2=Don’t care

C_IPIF_SPACETYPE_2=1

C_IPIFBAR_3=0x00000000

C_IPIF_HIGHADDR_3=0x0000007F

C_IPIFBAR2PCIBAR_3=Don’t care

C_IPIF SPACETYPE 3=1

Associated with each IPIF BAR for C IPIFBAR_N for N=0 to 3 are four registers for the high-order bits

to be substituted when making the translation to PCI memory and /IO space. For the previous example, the following registers are set.

Register for C IPIFBAR 0 (IPIFBAR2PCIBAR_0 High-Order Bit Register):

Programmable register for 16 high-order bits. The data in the register is substituted for the 16 msb of the address that is translated to PCI bus.

Register for C IPIFBAR 1 (IPIFBAR2PCIBAR_1 High-Order Bit Register):

Programmable register for 19 high-order bits. The data in the register is substituted for the 19 msb of the address that is translated to PCI bus.

Register for C IPIFBAR 2 (IPIFBAR2PCIBAR_2 High-Order Bit Register):

Programmable register for 7 high-order bits. The data in the register is substituted for the 7 msb of the address that is translated to PCI bus.

Register for C_IPIFBAR_3 (IPIFBAR2PCIBAR_3 High-Order Bit Register):

Programmable register for 25 high-order bits. The data in the register is substituted for the 25 msb of the address that is translated to PCI bus.

The remaining low-order bits are set to zero when a read of these registers is performed.

Writing 0x56710000 to IPIFBAR2PCIBAR_0 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus would yield 0x56710ABC on the PCI bus.

30	www.xilinx.com	DS508 March 21, 2006
		Product Specification

Image 30

Xilinx PLB PCI Full Bridge specifications CIPIFSPACETYPE0=1

Contents

Introduction LogiCORE Facts Features PLB PCI Full Bridge v1.00a PLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core Requirements Bus Interface Parameters Address Translation Example Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 Cplbawidth IPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0 Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOA Configuration V3.0 Core Parameters Group Ipif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System Signals Port Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0 PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1 V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code Name PLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr + Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers Descriptions Bits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicates PLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description Cincludebaroffsetreg CIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit bus Transaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchable Translation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target Perr PLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory Write Configuration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design Tools Design Debug Design Contraints NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 Support PLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision