Xilinx PLB PCI Full Bridge instruction

PLB PCI Full Bridge (v1.00a)

Table 8: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus) (Contd)

	Bit(s)	Name	Access	Reset	Description
	Bit(s)	Name	Access	Value	Description
				Value

		PLB Master	Read/Write		PLB Master Write Master Abort- Interrupt(25) indicates
	25	Write Master	Read/Write	0x0	that the PLB PCI Bridge asserted a PCI master abort due to
	25	Write Master	1 to clear	0x0	that the PLB PCI Bridge asserted a PCI master abort due to
		Abort	1 to clear		no response from a target.
		Abort			no response from a target.

		PLB Master	Read/Write		PLB Master Write Target Abort- Interrupt(26) indicates a
	26	Write Target	Read/Write	0x0	PCI target abort occurred during a PLB Master Write to a
	26	Write Target	1 to clear	0x0	PCI target abort occurred during a PLB Master Write to a
		Abort	1 to clear		PCI target.
		Abort			PCI target.

	27	PLB Master	Read/Write	0x0	PLB Master Write PERR- Interrupt(27) indicates a PERR
	27	Write PERR	1 to clear	0x0	error is detected on a PLB Master write to a PCI target.
		Write PERR	1 to clear		error is detected on a PLB Master write to a PCI target.

		PLB Master	Read/Write		PLB Master Write SERR- Interrupt(28) indicates that a
	28	PLB Master	Read/Write	0x0	SERR error was detected by the v3.0 core when performing
	28	Write SERR	1 to clear	0x0	SERR error was detected by the v3.0 core when performing
		Write SERR	1 to clear		as a PCI initiator writing data to a PCI target.
					as a PCI initiator writing data to a PCI target.

		PLB Master	Read/Write		PLB Master Read Target Abort- Interrupt(29) indicates
	29	Read Target	Read/Write	0x0	that a target abort was detected by the v3.0 core when
	29	Read Target	1 to clear	0x0	that a target abort was detected by the v3.0 core when
		Abort	1 to clear		performing as a PCI initiator reading data from a PCI target.
		Abort

		PLB Master	Read/Write		PLB Master Read PERR- Interrupt(30) indicates that a
	30	PLB Master	Read/Write	0x0	PERR was detected by the v3.0 core when performing as a
	30	Read PERR	1 to clear	0x0	PERR was detected by the v3.0 core when performing as a
		Read PERR	1 to clear		PCI initiator reading data from a PCI target.
					PCI initiator reading data from a PCI target.

		PLB Master	Read/Write		PLB Master Read SERR- Interrupt(31) indicates that a
	31	PLB Master	Read/Write	0x0	SERR error was detected by the v3.0 core when performing
	31	Read SERR	1 to clear	0x0	SERR error was detected by the v3.0 core when performing
		Read SERR	1 to clear		as a PCI initiator reading data from a PCI target.
					as a PCI initiator reading data from a PCI target.

Bridge Interrupt Enable Register Description

The PLB PCI Bridge has interrupt enable features as described in IPSPEC048 PLB Device Interrupt Architecture. Bit assignment in the Bridge Interrupt Enable Register is shown in Table 9. The interrupt enable register is read/write. All bits are cleared upon reset.

Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)

	Bit(s)	Name	Access	Reset			Description
	Bit(s)	Name	Access	Value			Description
				Value

	0-18		Read	0x0	Unassigned-

					PCI Initiator Write SERR Enable- Enables this interrupt to
	19	PCI Initiator	Read/Write	0x0	be passed to the interrupt controller.
	19	Write SERR	Read/Write	0x0	•	0	- Not enabled.
		Write SERR			•	0	- Not enabled.
					•	1	- Enabled.

					PCI Initiator Read SERR Enable- Enables this interrupt to
	20	PCI Initiator	Read/Write	0x0	be passed to the interrupt controller.
	20	Read SERR	Read/Write	0x0	•	0	- Not enabled.
		Read SERR			•	0	- Not enabled.
					•	1	- Enabled.

	21	Reserved		0x0	•	Reserved

		PLB Master			PLB Master Burst Write Retry Timeout Enable- Enables
		PLB Master			this interrupt to be passed to the interrupt controller.
	22	Write Retry	Read/Write	0x0	this interrupt to be passed to the interrupt controller.
	22	Write Retry	Read/Write	0x0	•	0	- Not enabled.
		Timeout			•	0	- Not enabled.
		Timeout			•	1	- Enabled.
					•	1	- Enabled.

26	www.xilinx.com	DS508 March 21, 2006
		Product Specification

Image 26

Xilinx PLB PCI Full Bridge specifications PLB Master Write Master Abort- Interrupt25 indicates

Contents

Introduction LogiCORE Facts Features PLB PCI Full Bridge v1.00a PLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core Requirements Bus Interface Parameters Address Translation Example Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 Cplbawidth IPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0 Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOA Configuration V3.0 Core Parameters Group Ipif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System Signals Port Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0 PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1 V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code Name PLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr + Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers Descriptions PLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicates PLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description IPIFBAR2PCIBARN High-Order Bits Register Description Cincludebaroffsetreg CIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit bus Transaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchable Translation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target Perr PLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Configuration Transactions Abnormal condition Memory Write Configuration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design Tools Design Debug Design Contraints NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 Support PLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History