Xilinx PLB PCI Full Bridge specifications - page 9

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 9
Product Specification
EARLY ACCESS
G13 IPIF BAR 2 memory
designator
C_IPIF_SPACE
TYPE_2
0 = I/O space
1 = Memory space 1integer
G14 IPIF device 3 BAR C_IPIFBAR_3 Valid PLB address (1), (2) 0xFFFFFFFF std_logic_
vector
G15 IPIF BAR high
address 3
C_IPIFBAR_
HIGHADDR_3 Valid PLB address (1), (2) 0x00000000 std_logic_ vector
G16
PCI BAR to which IPIF
BAR 3 is mapped
unless
C_INCLUDE_BAROFF
SET_REG = 1.
C_IPIFBAR2
PCIBAR_3
Vector of length
C_PLB_AWIDTH 0xFFFFFFFF std_logic_ vector
G17 IPIF BAR 3 memory
designator
C_IPIF_SPACE
TYPE_3
0 = I/O space
1 = Memory space 1integer
G18 IPIF device 4 BAR C_IPIFBAR_4 Valid PLB address (1), (2) 0xFFFFFFFF std_logic_
vector
G19 IPIF BAR high
address 4
C_IPIFBAR_
HIGHADDR_4 Valid PLB address (1), (2) 0x00000000 std_logic_ vector
G20
PCI BAR to which IPIF
BAR 4 is mapped
unless
C_INCLUDE_BAROFF
SET_REG = 1
C_IPIFBAR2
PCIBAR_4
Vector of length
C_PLB_AWIDTH 0xFFFFFFFF std_logic_ vector
G21 IPIF BAR 4 memory
designator
C_IPIF_SPACE
TYPE_4
0 = I/O space
1 = Memory space 1integer
G22 IPIF device 5 BAR C_IPIFBAR_5 Valid PLB address (1), (2) 0xFFFFFFFF std_logic_
vector
G23 IPIF BAR high
address 5
C_IPIFBAR_
HIGHADDR_5 Valid PLB address (1), (2) 0x00000000 std_logic_
vector
G24
PCI BAR to which IPIF
BAR 5 is mapped
unless
C_INCLUDE_BAROFF
SET_
REG = 1
C_IPIFBAR2
PCIBAR_5
Vector of length
C_PLB_AWIDTH 0xFFFFFFFF std_logic_ vector
G25 IPIF BAR 5 memory
designator
C_IPIF_SPACE
TYPE_5
0 = I/O space
1 = Memory space 1integer
G26 Number of PCI devices C_PCIBAR_
NUM
1-3; Parameters listed
below corresponding to
unused BARs are
ignored, but must be
valid values. BAR label
0 is the required bar for
all values 1-3 and the
index increments from 0
as BARs are added
3integer
Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic Feature /
Description
Parameter
Name Allowable Values Default Value
VHDL
Type