TYPE2, CIPIFBAR3, HIGHADDR3, TYPE3 | Xilinx PLB PCI Full Bridge

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

	Generic	Feature /	Parameter	Allowable Values	Default	VHDL
	Generic	Description	Name	Allowable Values	Value	Type
		Description	Name		Value	Type

	G13	IPIF BAR 2 memory	C_IPIF_SPACE	0 = I/O space	1	integer
	G13	designator	TYPE_2	1 = Memory space	1	integer
		designator	TYPE_2	1 = Memory space

	G14	IPIF device 3 BAR	C_IPIFBAR_3	Valid PLB address (1), (2)	0xFFFFFFFF	std_logic_
						vector

	G15	IPIF BAR high	C_IPIFBAR_	Valid PLB address (1), (2)	0x00000000	std_logic_
		address 3	HIGHADDR_3			vector

		PCI BAR to which IPIF
		BAR 3 is mapped	C_IPIFBAR2	Vector of length		std_logic_
	G16	unless	C_IPIFBAR2	Vector of length	0xFFFFFFFF	std_logic_
		C_INCLUDE_BAROFF	PCIBAR_3	C_PLB_AWIDTH		vector
		C_INCLUDE_BAROFF
		SET_REG = 1.

	G17	IPIF BAR 3 memory	C_IPIF_SPACE	0 = I/O space	1	integer
	G17	designator	TYPE_3	1 = Memory space	1	integer
		designator	TYPE_3	1 = Memory space

	G18	IPIF device 4 BAR	C_IPIFBAR_4	Valid PLB address (1), (2)	0xFFFFFFFF	std_logic_
						vector

	G19	IPIF BAR high	C_IPIFBAR_	Valid PLB address (1), (2)	0x00000000	std_logic_
		address 4	HIGHADDR_4			vector

		PCI BAR to which IPIF
		BAR 4 is mapped	C_IPIFBAR2	Vector of length		std_logic_
	G20	unless	C_IPIFBAR2	Vector of length	0xFFFFFFFF	std_logic_
		C_INCLUDE_BAROFF	PCIBAR_4	C PLB AWIDTH		vector
		C_INCLUDE_BAROFF
		SET_REG = 1

	G21	IPIF BAR 4 memory	C_IPIF_SPACE	0 = I/O space	1	integer
	G21	designator	TYPE_4	1 = Memory space	1	integer
		designator	TYPE_4	1 = Memory space

	G22	IPIF device 5 BAR	C IPIFBAR_5	Valid PLB address (1), (2)	0xFFFFFFFF	std_logic_
						vector

	G23	IPIF BAR high	C IPIFBAR_	Valid PLB address (1), (2)	0x00000000	std_logic_
		address 5	HIGHADDR_5			vector

		PCI BAR to which IPIF
		BAR 5 is mapped
	G24	unless	C IPIFBAR2	Vector of length	0xFFFFFFFF	std_logic_
		C_INCLUDE BAROFF	PCIBAR_5	C_PLB_AWIDTH		vector
		SET
		REG = 1

	G25	IPIF BAR 5 memory	C_IPIF_SPACE	0 = I/O space	1	integer
	G25	designator	TYPE_5	1 = Memory space	1	integer
		designator	TYPE_5	1 = Memory space

				1-3; Parameters listed
				below corresponding to
				unused BARs are
			C_PCIBAR_	ignored, but must be
	G26	Number of PCI devices	C_PCIBAR_	valid values. BAR label	3	integer
	G26	Number of PCI devices	NUM	valid values. BAR label	3	integer
			NUM	0 is the required bar for
				0 is the required bar for
				all values 1-3 and the
				index increments from 0
				as BARs are added

DS508 March 21, 2006

www.xilinx.com

9

Product Specification

Image 9

Xilinx PLB PCI Full Bridge TYPE2, CIPIFBAR3, HIGHADDR3, Cincludebaroff PCIBAR3 Cplbawidth, TYPE3, CIPIFBAR4, HIGHADDR4

Contents

LogiCORE Facts Introduction PLB PCI Full Bridge v1.00a Features PLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core Requirements Address Translation Bus Interface Parameters Example Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 Cplbawidth BAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0 Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOA V3.0 Core Parameters Group Configuration Ipif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System Signals Port Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0 PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1 V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code Name PLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr + PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter Dependencies Bits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicates PLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register Description CIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register Description Remote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchable Translation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI Target PLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration Transactions Configuration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design Implementation Design Contraints Design Debug NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target Technology PLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision