Xilinx PLB PCI Full Bridge specifications Introduction, LogiCORE Facts

	PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006					Product Specification
Introduction
			LogiCORE™ Facts
The PLB PCI Full Bridge design provides full bridge
				Core Specifics
functionality between the Xilinx 64-bit PLB and a 32-bit
	Supported Device				Virtex™-II Pro, Virtex-4
Revision 2.2 compliant Peripheral Component
	Family
Interconnect (PCI) bus. The bridge is referred to as the
	Version of Core				plb pci	v1.00a
PLB PCI Bridge in this document.
The Xilinx PLB is a 64-bit bus subset of the IBM PLB			Resources Used
described in the 64-Bit Processor Local Bus Architecture	Virtex-IIP				Min	Max
Specification v3.5. Details on the Xilinx PLB and the PLB
	I/O (PCI)				49	50
IPIF are found in the Processor IP Reference Guide. This
	I/O (PLB-related)				397	433
guide is accessed via EDK help or the Xilinx website at:
	LUTs				3350	3870
http://www.xilinx.com/ise/embedded/proc_ip_ref_
guide.pdf.
	FFs				2570	2970
The LogiCORE PCI v3.0 core provides an interface with					ESS
	Block RAMs				8	8
the PCI bus. Details of the LogiCORE PCI 32 v3.0 core
			Provided with Core
operation is found in the Xilinx LogiCORE PCI Interface		C
	Documentation				Product Specification
v3.0 Product Specification and the Xilinx The Real-PCI
Design Guide v3.0.	Design File Formats				VHDL
Host bridge functionality (often called North bridge	Constraints File				example UCF-file
functionality) is an optional functionality.
	Verification				N/A
Configuration Read and Write PCI commands can beAC					N/A
performed from the PLB-side of the bridge. The PLB	Instantiation Template
PCI Bridge supports a 32-bit/33 MHz PCI bus only.	Reference Designs				None
Exceptions to the support of PCI commands supported		Design Tool Requirements
by the v3.0 core are outlined in the Features section.
	Xilinx Implementation				8.1.1i or later
	Tools
The PLB PCI Bridge design has parameters that allow
customers to configure the bridge to suit their	Verification				N/A
application. The parameterizableRLYfeatures of the design
	Simulation				ModelSim SE/EE 5.8d or later
are discussed in the Bus Interface Parameters section.
A
E	Synthesis				XST
					Support
	Support provided by Xilinx, Inc.

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Product Specification