Xilinx PLB PCI Full Bridge specifications IPIFBAR2PCIBARN High-Order Bits Register Description

PLB PCI Full Bridge (v1.00a)

bus number. The highest subordinate bus number is also an 8-bit value. The fields are defined in Table 12. Reset clears all bits.

Table 12: Bus Number/Subordinate Bus Number Register Bit Definitions (Bit Assignment Assumes 32-bit

Bus)

Bit(s)	Name	Access	Reset	Description
			Value
0-7	D0- D7	Read	0x0	Reserved
8-15	D8 - D15	Read/Write	0x0	Bus number
16-23	D16 - D23	Read	0x0	Reserved
24-31	D24 - D31	Read/Write	0x0	Maximum subordinate bus number

IPIFBAR2PCIBAR_N High-Order Bits Register Description

When configured to include these registers (i.e., C INCLUDE BAROFFSET REG=1), the values in the registers are used to translate addresses on the PLB bus to the PCI. The register values are used instead of the corresponding parameter C_IPIFBAR2PCIBAR N for translation by high-order bit substitution. The parameters C_IPIFBAR2PCIBAR_N have no effect on the bridge operation if the registers for address translation are included.

The number of registers present is given by the number of IPIF BAR configured in the IPIF (i.e.,

C_IPIFBAR_NUM). The actual width of the Nth register is given by the number of high-order bits that define the complete address range corresponding to the Nth IPIF BAR. When the register is read, 32-bits are returned with the low-order bits hard-wired to zero.

The IPIFBAR2PCIBAR_N registers are included in the bridge via the parameter

C_INCLUDE_BAROFFSET_REG.

These read/write registers allow dynamic, run-time changes of the high-order bits for the substitution in the translation of an address from the PLB bus to the PCI bus. Low-order bits pass directly from the PLB bus to the PCI bus. When the register is read, 32-bits are read with the low-order bits set to zero. Table 13 shows the data format. The programmability of these registers allows PLB address transactions to access any target on the PCI bus which has been arbitrarily assigned a PCI BAR by a remote or local Host Bridge. Dynamic, run-time changes in the high-order bits for address translation of PLB PCI bridge PCI BAR range translation to PLB slaves is not needed because the PLB slave addresses are defined at build time.

Including these registers makes the parameters, C_IPIFBAR2PCIBAR_N, irrelevant because the value in the Nth programmable register replaces the values of the corresponding parameter, C_IPIFBAR2PCIBAR N, in translating the PLB address to the PCI bus. When the registers are included, the parameters, C IPIFBAR2PCIBAR_N, for N=0 to C_IPIFBAR_NUM-1, have no effect.

Table 13: IPIFBAR2PCIBAR N High-Order Bits (Bit assignment assumes 32-bit bus)

Bit(s)	Name	Access	Reset	Description
			Value
				M+1 high-order bits that are substituted in address
0-M	D0 - DM	Read/Write	0x0	translation from Nth IPIFBAR access to PCI address
				space
M+1-31	DM+1 - D31	Read Only	0x0	Low-order bits set to zero

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Product Specification