Texas Instruments SM320F2812-HT manuals
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Texas Instruments SM320F2812-HT Specifications
154 pages 1.38 Mb
2 SM320F2812-HTContents 3 SM320F2812-HT5 List of Figures7 List of Tables8 SM320F2812-HT11 Digital Signal Processor1 Features 12 SM320F2812-HT20 SM320F2812-HT28 SM320F2812-HTProduct Folder Link(s): SM320F2812-HT 3.1 Memory MapFigure 3-2. F2812 Memory Map (See Notes A. Through G.) 31 3.2 Brief Descriptions 3.2.1 C28x CPU3.2.2 Memory Bus (Harvard Bus Architecture) 3.2.3 Peripheral Bus 3.2.4 Real-Time JTAG and Analysis 32 SM320F2812-HT3.2.5 External Interface (XINTF) 3.2.6 Flash 3.2.7 L0, L1, H0 SARAMs 3.2.8 Boot ROM 33 3.2.9 Security34 3.2.10 Peripheral Interrupt Expansion (PIE) Block3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) 3.2.12 Oscillator and PLL 3.2.13 Watchdog 3.2.14 Peripheral Clocking 3.2.15 Low-Power Modes 35 3.2.16 Peripheral Frames 0, 1, 2 (PFn)3.2.17 General-Purpose Input/Output (GPIO) Multiplexer 3.2.18 32-Bit CPU Timers (0, 1, 2) 3.2.19 Control Peripherals 36 3.2.20 Serial Port Peripherals3.3 Register Map 39 3.4 Device Emulation Registers3.5 External Interface, XINTF 41 3.5.1 Timing Registers3.5.2 XREVISION Register 42 3.6 Interrupts45 3.6.1 External InterruptsTable 3-12. External Interrupts Registers 46 3.7 System Control48 3.8 OSC and PLL BlockFigure 3-7 shows the OSC and PLL block on the F2812. 49 3.8.1 Loss of Input Clock3.9 PLL-Based Clock Module 3.10 External Reference Oscillator Clock Option 50 3.11 Watchdog Block51 3.12 Low-Power Modes Block52 4 Peripherals78 Figure 4-11 is a block diagram of the SPI in slave mode. Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 79 4.8 GPIO MUX81 SM320F2812-HTFigure 4-12. GPIO/Peripheral Pin Multiplexing 82 5 Development Support85 6 Electrical Specifications6.1 Absolute Maximum Ratings 86 6.2 Recommended Operating Conditions6.3 Electrical CharacteristicsOver recommended operating conditions (unless otherwise noted) 88 HALT and STANDBY modes cannot be used when the PLL is disabled.88 Electrical Specifications 89 6.5 Current Consumption GraphsFigure 6-2. Typical Current Consumption Over Frequency Figure 6-3. Typical Power Consumption Over Frequency 90 6.6 Reducing Current Consumption6.7 Power Sequencing Requirements 91 6.8 Signal Transition Levels92 6.9 Timing Parameter Symbology93 6.10 General Notes on Timing Parameters6.11 Test Load Circuit 94 6.12 Device Clock Table6.13 Clock Requirements and Characteristics 6.13.1 Input Clock RequirementsTable 6-5. XCLKIN Timing Requirements PLL Bypassed or Enabled Table 6-6. XCLKIN Timing Requirements PLL Disabled Table 6-7. Possible PLL Configuration Modes 95 6.13.2 Output Clock CharacteristicsTable 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) Figure 6-8. Clock Timing 96 6.14 Reset Timing100 6.15 Low-Power Mode Wakeup Timing104 6.16 Event Manager Interface 6.16.1 PWM TimingPWM refers to all PWM outputs on EVA and EVB. 105 Table 6-13. PWM Switching CharacteristicsTable 6-14. Timer and Capture Unit Timing Requirements Figure 6-16. PWM Output Timing Figure 6-17. TDIRx Timing Table 6-15. External ADC Start-of-Conversion EVA Switching Characteristics Figure 6-19. EVBSOC Timing 106 6.16.2 Interrupt TimingTable 6-17. Interrupt Switching Characteristics Table 6-18. Interrupt Timing Requirements Figure 6-20. External Interrupt Timing 107 6.17 General-Purpose Input/Output (GPIO) Output TimingTable 6-19. General-Purpose Output Switching Characteristics Figure 6-21. General-Purpose Output Timing 108 6.18 General-Purpose Input/Output (GPIO) Input Timingtc(SPC) +SPI clock cycle time +LSPCLK 4or LSPCLK (SPIBRR)1) +tc(LCO) +LSPCLK cycle time (2) GPIOxn t XCLKOUT Figure 6-23. General-Purpose Input Timing 109 6.19 SPI Master Mode Timing113 6.20 SPI Slave Mode Timing117 6.21 External Interface (XINTF) Timing121 6.22 XINTF Signal Alignment to XCLKOUT122 6.23 External Interface Read TimingTable 6-34. External Memory Interface Read Switching Characteristics Table 6-35. External Memory Interface Read Timing Requirements Figure 6-29. Example Read Access 123 6.24 External Interface Write TimingTable 6-36. External Memory Interface Write Switching Characteristics Figure 6-30. Example Write Access 125 6.25 External Interface Ready-on-Read Timing With One External Wait State128 6.26 External Interface Ready-on-Write Timing With One External Wait State131 6.27 XHOLDand XHOLDA132 6.28 XHOLD/XHOLDATiming134 6.29 On-Chip Analog-to-Digital Converter 6.29.1 ADC Absolute Maximum Ratings135 6.29.2 ADC Electrical Characteristics Over Recommended Operating ConditionsTable 6-46. DC Specifications Table 6-47. AC Specifications 136 6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)Table 6-48. Current Consumption Figure 6-37. ADC Analog Input Impedance Model 137 6.29.4 ADC Power-Up Control Bit TimingFigure 6-38. ADC Power-Up Control Bit Timing Table 6-49. ADC Power-Up Delays 138 6.29.5 Detailed Description6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) 140 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)Figure 6-40. Simultaneous Sampling Mode Timing Table 6-51. Simultaneous Sampling Mode Timing 141 6.29.8 Definitions of Specifications and Terminology142 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing145 6.30.2 McBSP as SPI Master or Slave TimingTable 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 146 Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 147 Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 148 Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 149 6.31 Flash Timing 6.31.1 Recommended Operating Conditions151 7 Mechanical Data152 PACKAGE OPTION ADDENDUM
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