Texas Instruments SM320F2812-HT ADC Power-Up Control Bit Timing, ADCIN0, Pwdnbg Pwdnref, Pwdnadc

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

			Ron	Switch
	Rs	ADCIN0	1 kΩ
Source	ac		Cp
Signal			10 pF

Typical Values of the Input Circuit Components:

Switch Resistance (Ron):	1 kΩ
Sampling Capacitor (Ch):	1.25 pF
Parasitic Capacitance (Cp): 10 pF
Source Resistance (Rs):	50 Ω

Ch

1.25pF

28x DSP

Figure 6-37. ADC Analog Input Impedance Model

6.29.4 ADC Power-Up Control Bit Timing

ADC Power Up Delay ADC Ready for Conversions

PWDNBG

PWDNREF

td(BGR)

PWDNADC

td(PWD)

Request for

ADC

Conversion

Figure 6-38. ADC Power-Up Control Bit Timing

Table 6-49. ADC Power-Up Delays(1) (2)

		MIN	TYP
td(BGR)	Delay time for band gap reference to be stable. Bits 6 and 5 of the ADCTRL3 register	7	8
	(PWDNBG and PWDNREF) are to be set to 1 before the ADCPWDN bit is enabled.
td(PWD)	Delay time for power-down control to be stable. Bit 7 of the ADCTRL3 register (ADCPWDN)	20	50
	is to be set to 1 before any ADC conversions are initiated.

MAX	UNIT
10	ms
	μs
1	ms

(1)These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If conversions are started without these delays, the ADC results shows a higher gain. For power down, all three bits can be cleared at the same time.

(2)Not production tested.

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