SM320F2812-HT

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SGUS062A –JUNE 2009 –REVISED APRIL 2010

XCLKOUT

GPIOxn

tw(GPI)

Figure 6-23. General-Purpose Input Timing

NOTE

The pulse width requirement for general-purpose input is applicable for the XBIO and

ADCSOC pins as well.

6.19 SPI Master Mode Timing

Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3)

 

 

 

SPI WHEN (SPIBRR + 1)

SPI WHEN (SPIBRR + 1)

 

NO.

 

 

IS EVEN OR

 

IS ODD AND

 

UNIT

 

 

SPIBRR = 0 OR 2

 

SPIBRR > 3

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

 

MAX

MIN

 

MAX

 

1

tc(SPC)M

Cycle time, SPICLK

4tc(LCO)

 

128tc(LCO)

5tc(LCO)

 

127tc(LCO)

ns

 

tw(SPCH)M

Pulse duration, SPICLK high

0.5tc(SPC)M – 10

 

0.5tc(SPC)M

0.5tc(SPC)M – 0.5tc(LCO) – 10

 

0.5tc(SPC)M – 0.5tc(LCO)

 

 

(clock polarity = 0)

 

 

 

2(4)

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

tw(SPCL)M

Pulse duration, SPICLK low

0.5tc(SPC)M – 10

 

0.5tc(SPC)M

0.5tc(SPC)M – 0.5tc(LCO) – 10

 

0.5tc(SPC)M – 0.5tc(LCO)

 

 

 

 

 

(clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tw(SPCL)M

Pulse duration, SPICLK low

0.5tc(SPC)M – 10

 

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO) – 10

 

0.5tc(SPC)M + 0.5tc(LCO)

 

 

(clock polarity = 0)

 

 

 

3(4)

 

 

 

 

 

 

 

 

ns

tw(SPCH)M

Pulse duration, SPICLK high

0.5tc(SPC)M – 10

 

0.5tc(SPC)M

0.5tc(SPC)M + 0.5tc(LCO) – 10

 

0.5tc(SPC)M + 0.5tc(LCO)

 

(clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

td(SPCH-SIMO)M

Delay time, SPICLK high to SPISIMO

–10

 

10

–10

 

10

 

 

valid (clock polarity = 0)

 

 

 

4(4)

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

td(SPCL-SIMO)M

Delay time, SPICLK low to SPISIMO

–10

 

10

–10

 

10

 

 

 

 

 

valid (clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tv(SPCL-SIMO)M

Valid time, SPISIMO data valid after

0.5tc(SPC)M – 10

 

 

0.5tc(SPC)M + 0.5tc(LCO) – 10

 

 

 

 

SPICLK low (clock polarity = 0)

 

 

 

 

 

5(4)

 

 

 

 

 

 

 

ns

tv(SPCH-SIMO)M

Valid time, SPISIMO data valid after

0.5tc(SPC)M – 10

 

 

0.5tc(SPC)M + 0.5tc(LCO) – 10

 

 

 

SPICLK high (clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tsu(SOMI-SPCL)M

Setup time, SPISOMI before SPICLK

0

 

 

0

 

 

 

 

low (clock polarity = 0)

 

 

 

 

 

8(4)

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

tsu(SOMI-SPCH)M

Setup time, SPISOMI before SPICLK

0

 

 

0

 

 

 

 

 

 

 

 

 

high (clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tv(SPCL-SOMI)M

Valid time, SPISOMI data valid after

0.25tc(SPC)M – 10

 

 

0.5tc(SPC)M – 0.5tc(LCO) – 10

 

 

 

 

SPICLK low (clock polarity = 0)

 

 

 

 

 

9(4)

 

 

 

 

 

 

 

ns

tv(SPCH-SOMI)M

Valid time, SPISOMI data valid after

0.25tc(SPC)M – 10

 

 

0.5tc(SPC)M – 0.5tc(LCO) – 10

 

 

 

 

 

 

 

 

 

SPICLK high (clock polarity = 1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

t

c(SPC)

+ SPI clock cycle time +

LSPCLK or

LSPCLK

 

+ t

c(LCO)

+ LSPCLK cycle time

(SPIBRR ) 1)

(2)

 

4

 

 

 

 

 

 

 

 

 

 

(3)Not production tested.

(4)The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

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Texas Instruments SM320F2812-HT SPI Master Mode Timing, SPI Master Mode External Timing Clock Phase = 01 2, GPIOxn

SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

One of the standout features of the SM320F2812-HT is its robust architecture based on a 32-bit fixed-point core. This allows for efficient execution of complex algorithms while maintaining a high processing speed. The processor operates at clock speeds of up to 150 MHz, enabling it to handle multiple tasks simultaneously with minimal latency.

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