SPI Master Mode Timing, GPIOxn | Texas Instruments SM320F2812-HT

SM320F2812-HT

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SGUS062A –JUNE 2009 –REVISED APRIL 2010

XCLKOUT

GPIOxn

tw(GPI)

Figure 6-23. General-Purpose Input Timing

NOTE

The pulse width requirement for general-purpose input is applicable for the XBIO and

ADCSOC pins as well.

6.19 SPI Master Mode Timing

Table 6-21. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3)

			SPI WHEN (SPIBRR + 1)		SPI WHEN (SPIBRR + 1)
NO.			IS EVEN OR		IS ODD AND		UNIT
NO.			SPIBRR = 0 OR 2		SPIBRR > 3		UNIT

			MIN	MAX	MIN	MAX
1	tc(SPC)M	Cycle time, SPICLK	4tc(LCO)	128tc(LCO)	5tc(LCO)	127tc(LCO)	ns
	tw(SPCH)M	Pulse duration, SPICLK high	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M – 0.5tc(LCO) – 10	0.5tc(SPC)M – 0.5tc(LCO)
	tw(SPCH)M	(clock polarity = 0)	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M – 0.5tc(LCO) – 10	0.5tc(SPC)M – 0.5tc(LCO)
2(4)		(clock polarity = 0)					ns

	tw(SPCL)M	Pulse duration, SPICLK low	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M – 0.5tc(LCO) – 10	0.5tc(SPC)M – 0.5tc(LCO)
		Pulse duration, SPICLK low
		(clock polarity = 1)
		(clock polarity = 1)

	tw(SPCL)M	Pulse duration, SPICLK low	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)
	tw(SPCL)M	(clock polarity = 0)	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)
3(4)							ns
3(4)	tw(SPCH)M	Pulse duration, SPICLK high	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)	ns
	tw(SPCH)M	(clock polarity = 1)	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)
		(clock polarity = 1)
	td(SPCH-SIMO)M	Delay time, SPICLK high to SPISIMO	–10	10	–10	10
	td(SPCH-SIMO)M	valid (clock polarity = 0)	–10	10	–10	10
4(4)		valid (clock polarity = 0)					ns

	td(SPCL-SIMO)M	Delay time, SPICLK low to SPISIMO	–10	10	–10	10
		Delay time, SPICLK low to SPISIMO
		valid (clock polarity = 1)

	tv(SPCL-SIMO)M	Valid time, SPISIMO data valid after	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10
	tv(SPCL-SIMO)M	SPICLK low (clock polarity = 0)	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10
5(4)		SPICLK low (clock polarity = 0)					ns
5(4)	tv(SPCH-SIMO)M	Valid time, SPISIMO data valid after	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10		ns
	tv(SPCH-SIMO)M	SPICLK high (clock polarity = 1)	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10
		SPICLK high (clock polarity = 1)

	tsu(SOMI-SPCL)M	Setup time, SPISOMI before SPICLK	0		0
	tsu(SOMI-SPCL)M	low (clock polarity = 0)	0		0
8(4)		low (clock polarity = 0)					ns

	tsu(SOMI-SPCH)M	Setup time, SPISOMI before SPICLK	0		0
		Setup time, SPISOMI before SPICLK
		high (clock polarity = 1)

	tv(SPCL-SOMI)M	Valid time, SPISOMI data valid after	0.25tc(SPC)M – 10		0.5tc(SPC)M – 0.5tc(LCO) – 10
	tv(SPCL-SOMI)M	SPICLK low (clock polarity = 0)	0.25tc(SPC)M – 10		0.5tc(SPC)M – 0.5tc(LCO) – 10
9(4)		SPICLK low (clock polarity = 0)					ns
9(4)	tv(SPCH-SOMI)M	Valid time, SPISOMI data valid after	0.25tc(SPC)M – 10		0.5tc(SPC)M – 0.5tc(LCO) – 10		ns
		Valid time, SPISOMI data valid after
		SPICLK high (clock polarity = 1)
		SPICLK high (clock polarity = 1)

(1)The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

t	c(SPC)	+ SPI clock cycle time +	LSPCLK or	LSPCLK	+ t	c(LCO)	+ LSPCLK cycle time
				(SPIBRR ) 1)
(2)			4

(3)Not production tested.

(4)The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Copyright © 2009–2010, Texas Instruments Incorporated	Electrical Specifications	109
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SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

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Texas Instruments SM320F2812-HT specifications SPI Master Mode Timing, GPIOxn

Models: SM320F2812-HT