Texas Instruments SM320F2812-HT TX Fifo, Lspclk, Fsx, Clkx, XSR2 XSR1 RSR2 RSR1 Clkr, Fsr, Mrint

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

Figure 4-9shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of Peripheral Frame 2.

			Peripheral Write Bus
MXINT		TX FIFO	TX FIFO _15	TX FIFO _15
		Interrupt
To CPU	TX Interrupt Logic		—	—
			TX FIFO _1	TX FIFO _1
	McBSP Transmit		TX FIFO _0	TX FIFO _0
	Interrupt Select Logic		TX FIFO Registers
			16	16
LSPCLK		DXR2 Transmit Buffer		DXR1 Transmit Buffer
	McBSP Registers				FSX
			16	16
	and Control Logic			Compand Logic	CLKX
			XSR2	XSR1	DX
			RSR2	RSR1	DR
				16	CLKR
			16
				Expand Logic
					FSR
			RBR2 Register	RBR1 Register
			16	16
	McBSP		DRR2 Receive Buffer	DRR1 Receive Buffer
			16	16
	McBSP Receive		RX FIFO _15	RX FIFO _15
	Interrupt Select Logic
			—	—
MRINT	RX Interrupt Logic	RX FIFO	RX FIFO _1	RX FIFO _1
		Interrupt
To CPU			RX FIFO _0	RX FIFO _0
			RX FIFO Registers
			Peripheral Read Bus

Figure 4-9. McBSP Module With FIFO

70 Peripherals Copyright © 2009–2010, Texas Instruments Incorporated

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