Texas Instruments SM320F2812-HT Serial Communications Interface SCI Module Block Diagram

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

Figure 4-10shows the SCI module block diagram.

				SCICTL1.1
Frame Format and Mode					SCITXD	SCITXD
		TXSHF		TXENA
Parity		Register
Even/Odd	Enable			TX EMPTY
				SCICTL2.6
SCICCR.6	SCICCR.5	8
				TXRDY	TX INT ENA
		Transmitter−Data		SCICTL2.7
	TXWAKE	Buffer Register			SCICTL2.0
		8
	SCICTL1.3			TX FIFO		TXINT
		TX FIFO _0		Interrupts
	1				TX Interrupt
		TX FIFO _1
		−−−−−			Logic	To CPU
		TX FIFO _15		SCI TX Interrupt select logic
	WUT	SCITXBUF.7−0
		TX FIFO registers
		SCIFFENA		AutoBaud Detect logic
		SCIFFTX.14
SCIHBAUD. 15 − 8
Baud Rate		RXSHF			SCIRXD
						SCIRXD
		Register
	MSbyte
Register					RXWAKE
LSPCLK				SCIRXST.1
SCILBAUD. 7 − 0		RXENA
Baud Rate		8	SCICTL1.0
	LSbyte				SCICTL2.1
Register		Receive Data		RXRDY	RX/BK INT ENA
		Buffer register
		SCIRXBUF.7−0		SCIRXST.6
		8		BRKDT
		RX FIFO _15
		−−−−−		SCIRXST.5
		RX FIFO_1		RX FIFO
		RX FIFO _0		Interrupts		RXINT
					RX Interrupt
		SCIRXBUF.7−0
					Logic
		RX FIFO registers				To CPU
SCIRXST.7	SCIRXST.4 − 2	RXFFOVF
		SCIFFRX.15
RX Error	FE OE PE
RX Error
		RX ERR INT ENA		SCI RX Interrupt select logic
		SCICTL1.6

Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram

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