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Texas Instruments SM320F2812-HT specifications

Models: SM320F2812-HT

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SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

XTIMING register parameters used for this example:

XRDLEAD	XRDACTIVE	XRDTRAIL	USEREADY	X2TIMING	XWRLEAD	XWRACTIVE	XWRTRAIL	READYMODE

N/A(1)	N/A(1)	N/A(1)	0	0	≥ 1	≥ 0	≥ 0	N/A(1)

(1)N/A = "Don't care" for this example

124 Electrical SpecificationsCopyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments SM320F2812-HT specifications

Contents

Data Manual SM320F2812-HT Contents SM320F2812-HT PeripheralsSPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Digital Signal Processor Check for Samples SM320F2812-HTSupports Extreme Temperature Applications Introduction DescriptionHardware Features FeatureDevice Summary F2812Die Layout DIE PAD Backside DIE Size DIE PAD SizeCoordinates Thickness Finish Potential 55.0 x 64.0 μmPin Assignments SM320F2812 172-Pin HFG Cqfp Top ViewSignal Descriptions Signal Descriptions1Center Description HFG Xintf Signals PIN no DIE PADSignal Descriptions Center Description HFGCenter Description HFG Jtag and Miscellaneous Signals Trst TCKTMS TDICenter Description HFG ADC Analog Input Signals Center Description HFG Power Signals SM320F2812-HT Gpiob or EVB SignalsPeripheral PIN no DIE PAD Gpio DIE PAD no Signal HFG Center Gpiod or EVA SignalsGpiod or EVB Signals Gpioe or Interrupt SignalsGpiof or McBSP Signals Signal HFG Center Gpiof or can SignalsGpiof or XF CPU Output Signal GPIOG4 Scitxdb O Signal HFG Center Gpiog or SCI-B SignalsGPIOG5 Scirxdb Functional Overview Memory Map F2812 Memory Map See Notes A. Through GAddresses of Flash Sectors in F2812 Address Range Program and Data SpaceWait States AreaComments H0 SaramBrief Descriptions 1 C28x CPUMemory Bus Harvard Bus Architecture Peripheral BusBoot ROM External Interface XintfFlash 7 L0, L1, H0 SARAMsBoot Mode Selection Boot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2Security Code Security Module DisclaimerLow-Power Modes Peripheral Interrupt Expansion PIE BlockExternal Interrupts XINT1, XINT2, XINT13, Xnmi Oscillator and PLL18 32-Bit CPU Timers 0, 1 Peripheral Frames 0, 1, 2 PFnGeneral-Purpose Input/Output Gpio Multiplexer Control PeripheralsSerial Port Peripherals Register MapAccess Type Peripheral Frame 0 Registers1Peripheral Frame 1 Registers1 Name Address RangePeripheral Frame 2 Registers1 External Interface, Xintf Device Emulation RegistersDevice Emulation Registers XZCS0XZCS0AND1 XZCS1 XZCS2XZCS6 XZCS6AND7 XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda XclkoutXintf Configuration and Control Register Mappings Timing RegistersXrevision Register Xrevision Register Bit DefinitionsInterrupts Intm INT1 INT2 INT11 INT12CPU PIE Interrupts 11. PIE Configuration and Control Registers1 External Interrupts 12. External Interrupts RegistersClock and Reset Domains System Control13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL Block 14. Pllcr Register Bit DefinitionsPLL Mode Remarks Sysclkout Loss of Input ClockPLL-Based Clock Module External Reference Oscillator Clock OptionWatchdog Block Low-Power Modes Block 16. F2812 Low-Power ModesMode Oscclk Clkin Sysclkout32-Bit CPU-Timers 0/1/2 TddrhtddrPrdhprd Pschpsc TCR.4INT1 to INT12 C28x INT13 PIE TINT1 TINT0 CPU-TIMERINT14 XINT13 TINT2 CPU-Timers 0, 1, 2 Configuration and Control Registers Event Manager Modules EVA EVB Signal Module and Signal Names for EVA and EVBEvent Manager Modules EVA, EVB EVA Registers1 Event Manager a Functional Block Diagram See Note a General-Purpose GP Timers Double Update PWM ModeFull-Compare Units Programmable Deadband GeneratorPWM Characteristics Capture UnitQuadrature-Encoder Pulse QEP Circuit External ADC Start-of-ConversionEnhanced Analog-to-Digital Converter ADC Module Adcenclk Hspclk MUX ADCINA0ADCINA7 ADCADCINA70 ADCINB70Adclo Adcbgrefin ²Adclo Adcbgrefin SM320F2812-HTAvddrefbg Avssrefbg ADC Registers1 Enhanced Controller Area Network eCAN Module SN65HVD23x UnitCan Bus ECAN Memory Map Can Registers Map1 Register Name AddressWhere Clksrg source could be LSPCLK, CLKX, or CLKR.2 Multichannel Buffered Serial Port McBSP ModuleTX Fifo LspclkFSX ClkxName Address Type Reset Value Description McBSP Register SummaryHEX Data REGISTERS, RECEIVE, TransmitFifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-A Registers1 SCI-B Registers110. Serial Communications Interface SCI Module Block Diagram −−−−−Serial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−−11. Gpio Mux Registers1 2 Register Description12. Gpio Data Registers1 PIN Software Development Tools Device and Development Support Tool NomenclatureHardware Development Tools Documentation Support SM320F2812-HT Absolute Maximum Ratings Value UnitElectrical Characteristics Recommended Operating ConditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitDie Junction Temperature C HoursMode Test Conditions Current Consumption Graphs VddaioPower Sequencing Requirements Reducing Current ConsumptionPeripheral Module DD Current Reduction mARecommended Low-Dropout Regulators Signal Transition LevelsSupplier Part Number VOH 80% 20% VOL Timing Parameter SymbologyVIH 90% 10% VIL Test Load Circuit General Notes on Timing Parameters85 pF Clock Requirements and Characteristics Device Clock TableInput Clock Requirements Clock Table and NomenclatureOutput Clock Characteristics Xclkin Timing Requirements PLL Bypassed or EnabledXclkin Timing Requirements PLL Disabled1 Possible PLL Configuration Modes1Reset Timing Reset XRS Timing Requirements1XF/XPLLDIS GPIOF14Xclkout XRS XF/XPLLDIS XMP/MCXclkin Xclkout XRS XCLKIN/8GPIOF14/XF XCLKIN/2Low-Power Mode Wakeup Timing 10. Idle Mode Switching Characteristics1A0−A15 Xclkout = Sysclkout11. Standby Mode Switching Characteristics1 Device Status Flushing Pipeline Wake−up Signal StandbyXCLKOUT² Sysclkout Cycles12. Halt Mode Switching Characteristics1 Parameter MIN TYP MAX UnitEvent Manager Interface PWM Timing13. PWM Switching Characteristics1 14. Timer and Capture Unit Timing Requirements1Parameter Test Conditions MIN MAX Unit17. Interrupt Switching Characteristics Interrupt Timing19. General-Purpose Output Switching Characteristics General-Purpose Input/Output Gpio Output Timing18. Interrupt Timing Requirements TxCTRIP, CxTRIP PDPINTx See Note BQualprd Sysclkout General-Purpose Input/Output Gpio Input TimingQualprd = 1 2 x Sysclkout cycles x Output From Qualifier 21. SPI Master Mode External Timing Clock Phase = 01 2 SPI Master Mode TimingGPIOxn Spisimo Spisomi Master In Data Must Be Valid22. SPI Master Mode External Timing Clock Phase = 11 2 SM320F2812-HTData Valid SpisomiSPI Slave Mode Timing 23. SPI Slave Mode External Timing Clock Phase = 01 2SM320F2812-HT 24. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be ValidSM320F2812-HT 26. Xtiming Register Configuration Restrictions1 External Interface Xintf Timing27. Valid and Invalid Timing1 X2TIMING =29. Valid and Invalid Timing when using Synchronous XREADY1 28. Xtiming Register Configuration Restrictions130. Xtiming Register Configuration Restrictions1 31. Xtiming Register Configuration Restrictions1 33. Xintf Clock ConfigurationsMode Sysclkout Xtimclk Xclkout 32. Asynchronous XREADY128. Relationship Between Xtimclk and Sysclkout XINTCNF2 Clkoff Xtimclk ClkmodeXintf Signal Alignment to Xclkout XR/WExternal Interface Read Timing 35. External Memory Interface Read Timing Requirements1XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 XZCS6AND7External Interface Write Timing Lead ActiveXCLKOUT=XTIMCLK DoutSM320F2812-HT Setup time, Xready Synch low before Xclkout high/low DIN WS Synch Active Lead TrailXREADYSynch XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 WS AsynchXREADYAsynch Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access Xhold and Xholda XWE, XRD XZCS6AND7 XR/WXHOLD/XHOLDA Timing 44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2XR/W XZCS0AND1 XZCS2 XZCS6AND7XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk 36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 XtimclkOn-Chip Analog-to-Digital Converter ADC Absolute Maximum Ratings46. DC Specifications1 47. AC Specifications1 48. Current Consumption1MIN TYP MAX TYP ADC Operating MODE/CONDITIONSADC Power-Up Control Bit Timing ADCIN0Pwdnbg Pwdnref PwdnadcSequential Sampling Mode Single Channel Smode = Detailed DescriptionSample n + 50. Sequential Sampling Mode Timing1Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = AT 25-MHz ADCDefinitions of Specifications and Terminology Multichannel Buffered Serial Port McBSP Timing McBSP Transmit and Receive Timing52. McBSP Timing Requirements1 2 Clkg + Clksrg53. McBSP Switching Characteristics1 2 Dxena =M16 M18 M17 M18M1, M11 M2, M12 M13 M19Master Slave Unit MIN MAX McBSP as SPI Master or Slave TimingParameter Master Slave Unit MIN MAX M39 M49 M58 63. Flash/OTP Access Timing1 Flash TimingRecommended Operating Conditions 62. Flash Parameters at 150-MHz SYSCLKOUT1WAIT-STATE Random Wait STATE2 64. Minimum Required Wait-States at Different Frequencies250 Mechanical Data Orderable Device Package Type Pins Package Qty Eco Plan LeadSamples Page DSP Products ApplicationsRfid