Texas Instruments SM320F2812-HT McBSP as SPI Master or Slave Timing, Master Slave Unit MIN MAX

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

6.30.2 McBSP as SPI Master or Slave Timing

Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1)

NO.			MASTER	SLAVE		UNIT
			MIN MAX	MIN	MAX
M30	tsu(DRV0CKXL)	Setup time, DR valid before CLKX low	P – 10	8P – 10		ns
M31	th(CKXL0DRV)	Hold time, DR valid after CLKX low	P – 10	8P – 10		ns
M32	tsu(BFXL0CKXH)	Setup time, FSX low before CLKX high		8P + 10		ns
M33	tc(CKX)	Cycle time, CLKX	2P	16P		ns

(1)Not production tested.

Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)(1) (2)

NO.		PARAMETER	MASTER		SLAVE		UNIT
			MIN	MAX	MIN	MAX
M24	th(CKXL0FXL)	Hold time, FSX low after CLKX low	2P				ns
M25	td(FXL0CKXH)	Delay time, FSX low to CLKX high	P				ns
M28	tdis(FXH0DXHZ)	Disable time, DX high impedance following last data bit from	6		6P + 6		ns
		FSX high
M29	td(FXL0DXV)	Delay time, FSX low to DX valid	6		4P + 6		ns

(1)Not production tested.

(2)2P = 1/CLKG

For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns.

LSB M32 MSB M33

CLKX

	M24	M25
FSX
	M28	M29
DX	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		M30	M31
DR	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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