Texas Instruments SM320F2812-HT SM320F2812-HT

SM320F2812-HT

SGUS062A–JUNE 2009 –REVISED APRIL 2010

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single step through non-time critical code while enabling time-critical interrupts to be serviced without

interference. The F2812 implements the real-time mode in hardware within the CPU. This is a unique

feature to the F2812, no software monitor is required. Additionally, special analysis hardware is provided

which allows the user to set hardware breakpoint or data/address watch-points and generate various user

selectable break events when a match occurs.

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The

chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single

chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed

with a different number of wait states, strobe signal setup and hold timing and each zone can be

programmed for extending wait states externally or not. The programmable wait-state, chip-select, and

programmable strobe timing enables glueless interface to external memories and peripherals.

The F2812 contains 128K × 16 of embedded flash memory, segregated into four 8K × 16 sectors, and six

16K × 16 sectors. The F2810 has 64K × 16 of embedded flash, segregated into two 8K × 16 sectors, and

three 16K × 16 sectors. The device also contains a single 1K × 16 of OTP memory at address range 0x3D

7800 - 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving

other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute

flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the

flash module to achieve higher performance. The flash/OTP is mapped to both program and data space;

therefore, it can be used to execute code or store data information.

NOTE

The F2812 Flash and OTP wait states can be configured by the application. This allows

applications running at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution is much faster than the raw performance indicated by the wait state configuration

alone. The exact performance gain when using the Flash pipeline mode is

application-dependent. The pipeline mode is not available for the OTP block.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,

see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).

The F2812 contains an additional 16K × 16 of single-access RAM, divided into three blocks (4K + 4K +

8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to

both program and data space.

The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after

device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user

can select to execute code already present in the internal Flash or download new software to internal

RAM through one of several serial ports. Other boot modes exist as well. The Boot ROM also contains

standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-3 shows the

details of how various boot modes may be invoked. See the TMS320x281x DSP Boot ROM Reference

Guide (SPRS095), for more information.

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