Texas Instruments SM320F2812-HT Peripheral Frame 0 Registers1, Peripheral Frame 1 Registers1

				SM320F2812-HT
www.ti.com			SGUS062A –JUNE 2009 –REVISED APRIL 2010
	Table 3-4. Peripheral Frame 0 Registers(1)
NAME	ADDRESS RANGE	SIZE (× 16)		ACCESS TYPE (2)
Device Emulation Registers	0x00 0880	384		EALLOW protected
	0x00 09FF
reserved	0x00 0A00	128
	0x00 0A7F
FLASH Registers(3)	0x00 0A80	96		EALLOW protected
	0x00 0ADF			CSM Protected
Code Security Module Registers	0x00 0AE0	16		EALLOW protected
	0x00 0AEF
reserved	0x00 0AF0	48
	0x00 0B1F
XINTF Registers	0x00 0B20	32		Not EALLOW protected
	0x00 0B3F
reserved	0x00 0B40	192
	0x00 0BFF
CPU-TIMER0/1/2 Registers	0x00 0C00	64		Not EALLOW protected
	0x00 0C3F
reserved	0x00 0C40	160
	0x00 0CDF
PIE Registers	0x00 0CE0	32		Not EALLOW protected
	0x00 0CFF
PIE Vector Table	0x00 0D00	256		EALLOW protected
	0x00 0DFF
Reserved	0x00 0E00	512
	0x00 0FFF

(1)Registers in Frame 0 support 16-bit and 32-bit accesses.

(2)If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction disables writes. This prevents stray code or pointers from corrupting register contents.

(3)The Flash Registers are also protected by the Code Security Module (CSM).

Table 3-5. Peripheral Frame 1 Registers(1)

NAME	ADDRESS RANGE	SIZE (× 16)	ACCESS TYPE
eCAN Registers	0x00 6000	256	Some eCAN control registers (and selected bits in
	0x00 60FF	(128 × 32)	other eCAN control registers) are EALLOW-protected.
eCAN Mailbox RAM	0x00 6100	256	Not EALLOW-protected
	0x00 61FF	(128 × 32)
reserved	0x00 6200	3584
	0x00 6FFF

(1)The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.

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