Texas Instruments SM320F2812-HT specifications Fifo Mode Registers applicable only in Fifo mode

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

Table 4-7. McBSP Register Summary (continued)

NAME	ADDRESS	TYPE	RESET VALUE	DESCRIPTION
	0x00 78xxh	(R/W)	(HEX)
		FIFO MODE REGISTERS (applicable only in FIFO mode)
			FIFO Data Registers (1)
DRR2	00	R	0x0000	McBSP Data Receive Register 2 – Top of receive FIFO
				–Read First FIFO pointers does not advance
DRR1	01	R	0x0000	McBSP Data Receive Register 1 – Top of receive FIFO
				–Read Second for FIFO pointers to advance
DXR2	02	W	0x0000	McBSP Data Transmit Register 2 – Top of transmit FIFO
				–Write First FIFO pointers does not advance
DXR1	03	W	0x0000	McBSP Data Transmit Register 1 – Top of transmit FIFO
				–Write Second for FIFO pointers to advance
			FIFO Control Registers
MFFTX	20	R/W	0xA000	McBSP Transmit FIFO Register
MFFRX	21	R/W	0x201F	McBSP Receive FIFO Register
MFFCT	22	R/W	0x0000	McBSP FIFO Control Register
MFFINT	23	R/W	0x0000	McBSP FIFO Interrupt Register
MFFST	24	R/W	0x0000	McBSP FIFO Status Register

(1)FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.

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