Texas Instruments SM320F2812-HT Simultaneous Sampling Mode Dual-Channel Smode =, AT 25-MHz ADC

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)

In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels are sampled simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).

NOTE

In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, and not in other combinations (such as A1/B3, etc.).

Analog Input on

Channel Ax

Analog Input on

Channel Bv

ADC Clock

Sample and Hold

SH Pulse

SMODE Bit

ADC Event Trigger from

EV or Other Sources

Sample n

Sample n+1 Sample n+2

tSH	td(SH)		tdschA0_n+1
	tdschA0_n	t
		dschB0_n+1
	tdschB0_n

Figure 6-40. Simultaneous Sampling Mode Timing

Table 6-51. Simultaneous Sampling Mode Timing(1)

				AT 25-MHz ADC
		SAMPLE n	SAMPLE n + 1	CLOCK,	REMARKS
				tc(ADCCLK) = 40 ns
td(SH)	Delay time from event	2.5tc(ADCCLK)
	trigger to sampling
tSH	Sample/Hold	(1 + Acqps) ×		40 ns with Acqps = 0	Acqps value = 0–15
	width/Acquisition Width	tc(ADCCLK)			ADCTRL1[8:11]
	Delay time for first result
td(schA0_n)	to appear in Result	4tc(ADCCLK)		160 ns
	register
	Delay time for first result
td(schB0_n)	to appear in Result	5tc(ADCCLK)		200 ns
	register
	Delay time for successive		(3 + Acqps) ×
td(schA0_n+1)	results to appear in Result			120 ns
			tc(ADCCLK)
	register

(1)Not production tested.

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