Texas Instruments SM320F2812-HT PLL, Clocking, Watchdog, and Low-Power Mode Registers1

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

The PLL, clocking, watchdog, and low-power modes are controlled by the registers listed in Table 3-13.

Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers(1)

NAME	ADDRESS	SIZE (× 16)	DESCRIPTION
reserved	0x00 7010	8
	0x00 7017
reserved	0x00 7018	1
reserved	0x00 7019	1
HISPCP	0x00 701A	1	High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
LOSPCP	0x00 701B	1	Low-Speed Peripheral Clock Prescaler Register for LSPCLK clock
PCLKCR	0x00 701C	1	Peripheral Clock Control Register
reserved	0x00 701D	1
LPMCR0	0x00 701E	1	Low Power Mode Control Register 0
LPMCR1	0x00 701F	1	Low Power Mode Control Register 1
reserved	0x00 7020	1
PLLCR	0x00 7021	1	PLL Control Register(2)
SCSR	0x00 7022	1	System Control & Status Register
WDCNTR	0x00 7023	1	Watchdog Counter Register
reserved	0x00 7024	1
WDKEY	0x00 7025	1	Watchdog Reset Key Register
reserved	0x00 7026	3
	0x00 7028
WDCR	0x00 7029	1	Watchdog Control Register
reserved	0x00 702A	6
	0x00 702F

(1)All of the above registers can only be accessed by executing the EALLOW instruction.

(2)The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio) does not reset PLLCR.

Copyright © 2009–2010, Texas Instruments Incorporated	Functional Overview	47
	Submit Documentation Feedback

Product Folder Link(s): SM320F2812-HT