Data Manual
 SM320F2812-HT Contents
 Peripherals
SM320F2812-HT
 SPI Slave Mode Timing
 List of Figures
 General-Purpose Input Timing
 List of Tables
 Interrupt Switching Characteristics
 149
 Copyright 2009-2010, Texas Instruments Incorporated
 Check for Samples SM320F2812-HT
Digital Signal Processor
 Supports Extreme Temperature Applications
 Description
Introduction
 Feature
Hardware Features
Device Summary
F2812
 DIE PAD Backside DIE Size DIE PAD Size
Die Layout
Coordinates Thickness Finish Potential
55.0 x 64.0 μm
 SM320F2812 172-Pin HFG Cqfp Top View
Pin Assignments
 Signal Descriptions1
Signal Descriptions
Center Description HFG Xintf Signals
PIN no DIE PAD
 Center Description HFG
Signal Descriptions
 Center Description HFG Jtag and Miscellaneous Signals
 TCK
Trst
TMS
TDI
 Center Description HFG ADC Analog Input Signals
 Center Description HFG Power Signals
 Gpiob or EVB Signals
SM320F2812-HT
Peripheral PIN no DIE PAD Gpio DIE PAD no
 Gpiod or EVA Signals
Signal HFG Center
Gpiod or EVB Signals
Gpioe or Interrupt Signals
 Signal HFG Center Gpiof or can Signals
Gpiof or McBSP Signals
Gpiof or XF CPU Output Signal
 Signal HFG Center Gpiog or SCI-B Signals
GPIOG4 Scitxdb O
GPIOG5 Scirxdb
 Functional Overview
 F2812 Memory Map See Notes A. Through G
Memory Map
 Address Range Program and Data Space
Addresses of Flash Sectors in F2812
 Area
Wait States
Comments
H0 Saram
 1 C28x CPU
Brief Descriptions
Memory Bus Harvard Bus Architecture
Peripheral Bus
 External Interface Xintf
Boot ROM
Flash
7 L0, L1, H0 SARAMs
 Boot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2
Boot Mode Selection
Security
Code Security Module Disclaimer
 Peripheral Interrupt Expansion PIE Block
Low-Power Modes
External Interrupts XINT1, XINT2, XINT13, Xnmi
Oscillator and PLL
 Peripheral Frames 0, 1, 2 PFn
18 32-Bit CPU Timers 0, 1
General-Purpose Input/Output Gpio Multiplexer
Control Peripherals
 Register Map
Serial Port Peripherals
 Peripheral Frame 0 Registers1
Access Type
Peripheral Frame 1 Registers1
Name Address Range
 Peripheral Frame 2 Registers1
 Device Emulation Registers
External Interface, Xintf
Device Emulation Registers
 XZCS2
XZCS0XZCS0AND1 XZCS1
XZCS6 XZCS6AND7
XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda Xclkout
 Timing Registers
Xintf Configuration and Control Register Mappings
Xrevision Register
Xrevision Register Bit Definitions
 Interrupts
 INT1 INT2 INT11 INT12
Intm
CPU PIE Interrupts
 11. PIE Configuration and Control Registers1
 12. External Interrupts Registers
External Interrupts
 System Control
Clock and Reset Domains
 13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1
 14. Pllcr Register Bit Definitions
OSC and PLL Block
 Loss of Input Clock
PLL Mode Remarks Sysclkout
PLL-Based Clock Module
External Reference Oscillator Clock Option
 Watchdog Block
 16. F2812 Low-Power Modes
Low-Power Modes Block
Mode
Oscclk Clkin Sysclkout
 Tddrhtddr
32-Bit CPU-Timers 0/1/2
Prdhprd
Pschpsc TCR.4
 INT13 PIE TINT1 TINT0 CPU-TIMER
INT1 to INT12 C28x
INT14 XINT13 TINT2
 CPU-Timers 0, 1, 2 Configuration and Control Registers
 Module and Signal Names for EVA and EVB
Event Manager Modules EVA EVB Signal
Event Manager Modules EVA, EVB
 EVA Registers1
 Event Manager a Functional Block Diagram See Note a
 Double Update PWM Mode
General-Purpose GP Timers
Full-Compare Units
Programmable Deadband Generator
 Capture Unit
PWM Characteristics
Quadrature-Encoder Pulse QEP Circuit
External ADC Start-of-Conversion
 Enhanced Analog-to-Digital Converter ADC Module
 MUX ADCINA0
Adcenclk Hspclk
ADCINA7
ADC
 ADCINB70
ADCINA70
Adclo
Adcbgrefin ²
 SM320F2812-HT
Adclo Adcbgrefin
Avddrefbg Avssrefbg
 ADC Registers1
 Enhanced Controller Area Network eCAN Module
 Unit
SN65HVD23x
Can Bus
 ECAN Memory Map
 Register Name Address
Can Registers Map1
 Multichannel Buffered Serial Port McBSP Module
Where Clksrg source could be LSPCLK, CLKX, or CLKR.2
 Lspclk
TX Fifo
FSX
Clkx
 McBSP Register Summary
Name Address Type Reset Value Description
HEX
Data REGISTERS, RECEIVE, Transmit
 Fifo Mode Registers applicable only in Fifo mode
 Serial Communications Interface SCI Module
 SCI-B Registers1
SCI-A Registers1
 −−−−−
10. Serial Communications Interface SCI Module Block Diagram
 Serial Peripheral Interface SPI Module
 10. SPI Registers1
 −−−−−
−−−−−
 Register Description
11. Gpio Mux Registers1 2
 12. Gpio Data Registers1
 PIN
 Device and Development Support Tool Nomenclature
Software Development Tools
Hardware Development Tools
 Documentation Support
 SM320F2812-HT
 Value Unit
Absolute Maximum Ratings
 Recommended Operating Conditions
Electrical Characteristics
MIN NOM MAX Unit
Parameter Test Conditions MIN TYP MAX Unit
 Hours
Die Junction Temperature C
 Mode Test Conditions
 Vddaio
Current Consumption Graphs
 Reducing Current Consumption
Power Sequencing Requirements
Peripheral Module
DD Current Reduction mA
 Signal Transition Levels
Recommended Low-Dropout Regulators
Supplier Part Number
 Timing Parameter Symbology
VOH 80% 20% VOL
VIH 90% 10% VIL
 General Notes on Timing Parameters
Test Load Circuit
85 pF
 Device Clock Table
Clock Requirements and Characteristics
Input Clock Requirements
Clock Table and Nomenclature
 Xclkin Timing Requirements PLL Bypassed or Enabled
Output Clock Characteristics
Xclkin Timing Requirements PLL Disabled1
Possible PLL Configuration Modes1
 Reset XRS Timing Requirements1
Reset Timing
 GPIOF14
XF/XPLLDIS
 XF/XPLLDIS XMP/MC
Xclkout XRS
 XCLKIN/8
Xclkin Xclkout XRS
GPIOF14/XF
XCLKIN/2
 10. Idle Mode Switching Characteristics1
Low-Power Mode Wakeup Timing
A0−A15
Xclkout = Sysclkout
 11. Standby Mode Switching Characteristics1
 Standby
Device Status Flushing Pipeline Wake−up Signal
XCLKOUT²
Sysclkout Cycles
 12. Halt Mode Switching Characteristics1
 PWM Timing
Event Manager Interface
 14. Timer and Capture Unit Timing Requirements1
13. PWM Switching Characteristics1
Parameter Test Conditions MIN
MAX Unit
 Interrupt Timing
17. Interrupt Switching Characteristics
 General-Purpose Input/Output Gpio Output Timing
19. General-Purpose Output Switching Characteristics
18. Interrupt Timing Requirements
TxCTRIP, CxTRIP PDPINTx See Note B
 General-Purpose Input/Output Gpio Input Timing
Qualprd Sysclkout
Qualprd = 1 2 x Sysclkout cycles x Output From Qualifier
 SPI Master Mode Timing
21. SPI Master Mode External Timing Clock Phase = 01 2
GPIOxn
 Spisomi Master In Data Must Be Valid
Spisimo
 22. SPI Master Mode External Timing Clock Phase = 11 2
 Spisomi
Data Valid
 23. SPI Slave Mode External Timing Clock Phase = 01 2
SPI Slave Mode Timing
 SM320F2812-HT
 Spisimo Data Must Be Valid
24. SPI Slave Mode External Timing Clock Phase = 11 2
 SM320F2812-HT
 External Interface Xintf Timing
26. Xtiming Register Configuration Restrictions1
27. Valid and Invalid Timing1
X2TIMING =
 28. Xtiming Register Configuration Restrictions1
29. Valid and Invalid Timing when using Synchronous XREADY1
30. Xtiming Register Configuration Restrictions1
 33. Xintf Clock Configurations
31. Xtiming Register Configuration Restrictions1
Mode Sysclkout Xtimclk Xclkout
32. Asynchronous XREADY1
 XINTCNF2 Clkoff Xtimclk Clkmode
28. Relationship Between Xtimclk and Sysclkout
 XR/W
Xintf Signal Alignment to Xclkout
 35. External Memory Interface Read Timing Requirements1
External Interface Read Timing
XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk
XZCS0AND1, XZCS2 XZCS6AND7
 Lead Active
External Interface Write Timing
XCLKOUT=XTIMCLK
Dout
 SM320F2812-HT
 Setup time, Xready Synch low before Xclkout high/low
 WS Synch Active Lead Trail
DIN
XREADYSynch
 WS Asynch
XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2
XREADYAsynch
 Parameter MIN MAX Unit
 33. Write With Synchronous Xready Access
 34. Write With Asynchronous Xready Access
 XWE, XRD XZCS6AND7 XR/W
Xhold and Xholda
 44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2
XHOLD/XHOLDA Timing
XR/W XZCS0AND1
XZCS2 XZCS6AND7
 36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk
XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk
 ADC Absolute Maximum Ratings
On-Chip Analog-to-Digital Converter
 46. DC Specifications1
 48. Current Consumption1
47. AC Specifications1
MIN TYP MAX
TYP ADC Operating MODE/CONDITIONS
 ADCIN0
ADC Power-Up Control Bit Timing
Pwdnbg Pwdnref
Pwdnadc
 Detailed Description
Sequential Sampling Mode Single Channel Smode =
 50. Sequential Sampling Mode Timing1
Sample n +
Clock Remarks
 AT 25-MHz ADC
Simultaneous Sampling Mode Dual-Channel Smode =
 Definitions of Specifications and Terminology
 McBSP Transmit and Receive Timing
Multichannel Buffered Serial Port McBSP Timing
52. McBSP Timing Requirements1 2
Clkg + Clksrg
 Dxena =
53. McBSP Switching Characteristics1 2
 M17 M18
M16 M18
M1, M11 M2, M12 M13
M19
 McBSP as SPI Master or Slave Timing
Master Slave Unit MIN MAX
Parameter Master Slave Unit MIN MAX
 M39
 M49
 M58
 Flash Timing
63. Flash/OTP Access Timing1
Recommended Operating Conditions
62. Flash Parameters at 150-MHz SYSCLKOUT1
 64. Minimum Required Wait-States at Different Frequencies
WAIT-STATE Random Wait STATE2
250
 Mechanical Data
 Package Type Pins Package Qty Eco Plan Lead
Orderable Device
Samples
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