Texas Instruments SM320F2812-HT specifications Write With Asynchronous Xready Access

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010			www.ti.com
	WS (Asynch)
See Notes		Trail	See Note C
	Active
A and B
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)		td(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7		th(XRDYasynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
	td(XCOHL-XWEL)	td(XCOHL-XWEH)
XWE
td(XCOH-XRNWL)		td(XCOHL-XRNWH)
XR/W
	td(XWEL-XD	tdis(XD)XRNW
ten(XD)XWEL	)	th(XD)XWEH
XD[0:15]		DOUT

tsu(XRDYasynchL)XCOHL

th(XRDYasynchL) te(XRDYasynchH)

tsu(XRDYasynchH)XCOHL

XREADY(Asynch)

See Note D

See Note E

Legend:

= Don't care. Signal can be high or low during this time.

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement.

B.During alignment cycles, all signals transitions to their inactive state.

C.During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

D.For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE −3 + n) t c(XTIM) − t su(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3 and so forth.

E.Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE −2) t c(XTIM)

Figure 6-34. Write With Asynchronous XREADY Access

XTIMING register parameters used for this example:

XRDLEAD	XRDACTIVE	XRDTRAIL	USEREADY	X2TIMING	XWRLEAD	XWRACTIVE	XWRTRAIL	READYMODE
N/A(1)	N/A(1)	N/A(1)	1	0	≥ 1	3	≥ 1	1 = XREADY
								(Asynch)

(1)N/A = "Don't care" for this example

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