Texas Instruments SM320F2812-HT Multichannel Buffered Serial Port McBSP Timing, Clkg + Clksrg

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

6.30 Multichannel Buffered Serial Port (McBSP) Timing

6.30.1 McBSP Transmit and Receive Timing

Table 6-52. McBSP Timing Requirements(1) (2) (3)

NO.				MIN	MAX	UNIT
		McBSP module clock (CLKG, CLKX, CLKR) range		1		kHz
					20(4)	MHz
		McBSP module cycle time (CLKG, CLKX, CLKR) range		50		ns
					1	ms
M11	tc(CKRX)	Cycle time, CLKR/X	CLKR/X ext	2P		ns
M12	tw(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	P–7		ns
M13	tr(CKRX)	Rise time, CLKR/X	CLKR/X ext		7	ns
M14	tf(CKRX)	Fall time, CLKR/X	CLKR/X ext		7	ns
M15	tsu(FRH-CKRL)	Setup time, external FSR high before CLKR low	CLKR int	18		ns
			CLKR ext	2
M16	th(CKRL-FRH)	Hold time, external FSR high after CLKR low	CLKR int	0		ns
			CLKR ext	6
M17	tsu(DRV-CKRL)	Setup time, DR valid before CLKR low	CLKR int	18		ns
			CLKR ext	2
M18	th(CKRL-DRV)	Hold time, DR valid after CLKR low	CLKR int	0		ns
			CLKR ext	6
M19	tsu(FXH-CKXL)	Setup time, external FSX high before CLKX low	CLKX int	18		ns
			CLKX ext	2
M20	th(CKXL-FXH)	Hold time, external FSX high after CLKX low	CLKX int	0		ns
			CLKX ext	6

(1)Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

CLKG +	CLKSRG
	(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux.

CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.

(3)Not production tested.

(4)Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (20 MHz).

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