Texas Instruments SM320F2812-HT External Interface Read Timing, XZCS0AND1, XZCS2 XZCS6AND7

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

6.23 External Interface Read Timing

Table 6-34. External Memory Interface Read Switching Characteristics(1)

	PARAMETER				MIN	MAX	UNIT
td(XCOH-XZCSL)	Delay time, XCLKOUT high to zone chip-select active low					1	ns
td(XCOHL-XZCSH)	Delay time, XCLKOUT high/low to zone chip-select inactive high				–2	3	ns
td(XCOH-XA)	Delay time, XCLKOUT high to address valid					2	ns
td(XCOHL-XRDL)	Delay time, XCLKOUT high/low to		active low			1	ns
		XRD
td(XCOHL-XRDH	Delay time, XCLKOUT high/low to			inactive high	–2	1	ns
		XRD
th(XA)XZCSH	Hold time, address valid after zone chip-select inactive high				(2)		ns
					(2)
th(XA)XRD	Hold time, address valid after XRD inactive high						ns

(1)Not production tested.

(2)During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

Table 6-35. External Memory Interface Read Timing Requirements(1)

								MIN	MAX		UNIT
t	Access time, read data from address valid								(LR + AR) – 14	(2)	ns
a(A)
t	Access time, read data valid from					active low			AR – 12	(2)	ns
			XRD
a(XRD)
tsu(XD)XRD	Setup time, read data valid before						strobe inactive high	12			ns
				XRD
th(XD)XRD	Hold time, read data valid after				inactive high			0			ns
		XRD

(1)Not production tested.

(2)LR = Lead period, read access. AR = Active period, read access. See Table 6-25 .

XCLKOUT=XTIMCLK

XCLKOUT= 1/2 XTIMCLK

Lead

Trail

Active

XZCS0AND1, XZCS2,

XZCS6AND7

XA[0:18]

td(XCOH-XZCSL)

td(XCOH-XA)

td(XCOHL-XZCSH)

XRD

XWE

XR/W

XD[0:15]

td(XCOHL-XRDL)	td(XCOHL-XRDH)
	tsu(XD)XRD
ta(A)
ta(XRD)	th(XD)XRD

DIN

XREADY

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement.

B.During alignment cycles, all signals transitions to their inactive state.

C.For USEREADY = 0, the external XREADY input signal is ignored.

D.XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

Figure 6-29. Example Read Access

122 Electrical Specifications Copyright © 2009–2010, Texas Instruments Incorporated

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